From: Kishon Vijay Abraham I <kishon@ti.com>
To: <gregkh@linuxfoundation.org>
Cc: <kishon@ti.com>, <linux-kernel@vger.kernel.org>
Subject: [PATCH 09/25] phy: berlin-sata: Move PHY_BASE into private data struct
Date: Thu, 27 Nov 2014 11:56:01 +0530 [thread overview]
Message-ID: <1417069577-1169-10-git-send-email-kishon@ti.com> (raw)
In-Reply-To: <1417069577-1169-1-git-send-email-kishon@ti.com>
From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Currently, Berlin SATA PHY driver assumes PHY_BASE address being
constant. While this PHY_BASE is correct for BG2Q, older BG2 PHY_BASE
is different. Prepare the driver for BG2 support by moving the phy_base
into private driver data.
Acked-by: Antoine Ténart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/phy/phy-berlin-sata.c | 24 +++++++++++++++---------
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/phy-berlin-sata.c b/drivers/phy/phy-berlin-sata.c
index 69ced52..cdb46d1 100644
--- a/drivers/phy/phy-berlin-sata.c
+++ b/drivers/phy/phy-berlin-sata.c
@@ -30,7 +30,7 @@
#define MBUS_WRITE_REQUEST_SIZE_128 (BIT(2) << 16)
#define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19)
-#define PHY_BASE 0x200
+#define BG2Q_PHY_BASE 0x200
/* register 0x01 */
#define REF_FREF_SEL_25 BIT(0)
@@ -61,15 +61,16 @@ struct phy_berlin_priv {
struct clk *clk;
struct phy_berlin_desc **phys;
unsigned nphys;
+ u32 phy_base;
};
-static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg, u32 reg,
- u32 mask, u32 val)
+static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg,
+ u32 phy_base, u32 reg, u32 mask, u32 val)
{
u32 regval;
/* select register */
- writel(PHY_BASE + reg, ctrl_reg + PORT_VSR_ADDR);
+ writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR);
/* set bits */
regval = readl(ctrl_reg + PORT_VSR_DATA);
@@ -103,17 +104,20 @@ static int phy_berlin_sata_power_on(struct phy *phy)
writel(regval, priv->base + HOST_VSA_DATA);
/* set PHY mode and ref freq to 25 MHz */
- phy_berlin_sata_reg_setbits(ctrl_reg, 0x1, 0xff,
- REF_FREF_SEL_25 | PHY_MODE_SATA);
+ phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,
+ 0x00ff, REF_FREF_SEL_25 | PHY_MODE_SATA);
/* set PHY up to 6 Gbps */
- phy_berlin_sata_reg_setbits(ctrl_reg, 0x25, 0xc00, PHY_GEN_MAX_6_0);
+ phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,
+ 0x0c00, PHY_GEN_MAX_6_0);
/* set 40 bits width */
- phy_berlin_sata_reg_setbits(ctrl_reg, 0x23, 0xc00, DATA_BIT_WIDTH_40);
+ phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23,
+ 0x0c00, DATA_BIT_WIDTH_40);
/* use max pll rate */
- phy_berlin_sata_reg_setbits(ctrl_reg, 0x2, 0x0, USE_MAX_PLL_RATE);
+ phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02,
+ 0x0000, USE_MAX_PLL_RATE);
/* set Gen3 controller speed */
regval = readl(ctrl_reg + PORT_SCR_CTL);
@@ -218,6 +222,8 @@ static int phy_berlin_sata_probe(struct platform_device *pdev)
if (!priv->phys)
return -ENOMEM;
+ priv->phy_base = BG2Q_PHY_BASE;
+
dev_set_drvdata(dev, priv);
spin_lock_init(&priv->lock);
--
1.7.9.5
next prev parent reply other threads:[~2014-11-27 6:31 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-27 6:25 [GIT PULL 00/25] phy: for 3.19 Kishon Vijay Abraham I
2014-11-27 6:25 ` [PATCH 01/25] phy: Add PHY header file for DT x Driver defines Kishon Vijay Abraham I
2014-11-27 6:25 ` [PATCH 02/25] phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp Kishon Vijay Abraham I
2014-11-27 6:25 ` [PATCH 03/25] phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY Kishon Vijay Abraham I
2014-11-27 7:00 ` sanjeev sharma
2014-11-27 6:25 ` [PATCH 04/25] phy: miphy28lp: Add SSC support for SATA Kishon Vijay Abraham I
2014-11-27 6:25 ` [PATCH 05/25] phy: miphy28lp: Add SSC support for PCIE Kishon Vijay Abraham I
2014-11-27 6:25 ` [PATCH 06/25] phy: miphy28lp: Tune tx impedance across Soc cuts Kishon Vijay Abraham I
2014-11-27 6:25 ` [PATCH 07/25] phy: phy-core: use the np present in of_phandle_args to get the PHY Kishon Vijay Abraham I
2014-11-27 6:26 ` [PATCH 08/25] phy: sun4i: add support for USB phy0 Kishon Vijay Abraham I
2014-11-27 6:26 ` Kishon Vijay Abraham I [this message]
2014-11-27 6:26 ` [PATCH 10/25] phy: berlin-sata: Add support for BG2 SATA PHY Kishon Vijay Abraham I
2014-11-27 6:26 ` [PATCH 11/25] phy: berlin-sata: Document BG2 compatible Kishon Vijay Abraham I
2014-11-27 6:26 ` [PATCH 12/25] phy: add the Berlin USB PHY driver Kishon Vijay Abraham I
2014-11-27 6:26 ` [PATCH 13/25] Documentation: bindings: add doc for the Berlin USB PHY Kishon Vijay Abraham I
2014-11-27 6:26 ` [PATCH 14/25] phy: safer to_phy() macro Kishon Vijay Abraham I
2014-11-27 6:26 ` [PATCH 15/25] phy: improved lookup method Kishon Vijay Abraham I
2014-11-27 6:26 ` [PATCH 16/25] phy: twl4030: use the new " Kishon Vijay Abraham I
2014-11-27 6:26 ` [PATCH 17/25] phy: remove the old " Kishon Vijay Abraham I
2014-11-27 6:26 ` [PATCH 18/25] usb: dwc3: host: convey the PHYs to xhci Kishon Vijay Abraham I
2014-11-27 6:26 ` [PATCH 19/25] phy: exynos5-usbdrd: Add pipe-clk, utmi-clk and itp-clk support Kishon Vijay Abraham I
2014-11-27 6:26 ` [PATCH 20/25] phy: exynos5-usbdrd: Add facility for VBUS-BOOST-5V supply Kishon Vijay Abraham I
2014-11-27 6:26 ` [PATCH 21/25] phy: exynos7-usbdrd: Update dependency for ARCH_EXYNOS Kishon Vijay Abraham I
2014-11-27 6:26 ` [PATCH 22/25] phy: Use PTR_ERR_OR_ZERO to fix warning raised by coccinelle Kishon Vijay Abraham I
2014-11-27 6:26 ` [PATCH 23/25] Phy: DT binding documentation for Marvell MVEBU SATA phy Kishon Vijay Abraham I
2014-11-27 6:26 ` [PATCH 24/25] Phy: DT binding documentation for the Armada 375 USB cluster binding Kishon Vijay Abraham I
2014-11-27 6:26 ` [PATCH 25/25] phy: add support for USB cluster on the Armada 375 SoC Kishon Vijay Abraham I
2014-11-27 16:49 ` [GIT PULL 00/25] phy: for 3.19 Greg KH
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