* Re: [PATCH v2 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table
[not found] <1472569320.5703.23.camel@toradex.com>
@ 2016-08-31 7:17 ` Marcel Ziswiler
0 siblings, 0 replies; 2+ messages in thread
From: Marcel Ziswiler @ 2016-08-31 7:17 UTC (permalink / raw)
To: jonathanh, mirza.krak, swarren, thierry.reding
Cc: linux-kernel, robh+dt, mturquette, pgaikwad, linux, devicetree,
gnurou, mark.rutland, linux-arm-kernel, pdeschrijver, sboyd,
linux-tegra, linux-clk
On Wed, 2016-08-24 at 15:37 +0200, Mirza Krak wrote:
>
> From: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz
> which
> is max rate.
>
> Signed-off-by: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.g
> mane.org>
> ---
> Changes in v2:
> - no changes
>
> drivers/clk/tegra/clk-tegra30.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-
> tegra30.c
> index 8e2db5e..67f1677 100644
> --- a/drivers/clk/tegra/clk-tegra30.c
> +++ b/drivers/clk/tegra/clk-tegra30.c
> @@ -1252,6 +1252,7 @@ static struct tegra_clk_init_table init_table[]
> __initdata = {
> { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
> { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
> { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
> + { TEGRA30_CLK_NOR, TEGRA30_CLK_PLL_P, 127000000, 0 },
The Tegra 3 Interface Design Guide states the same 133 MHz.
>
> { TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 },
> { TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1 },
> { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
> --
> 2.1.4
^ permalink raw reply [flat|nested] 2+ messages in thread
* [PATCH v2 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table
2016-08-24 13:37 [PATCH v2 0/6] Add support for Tegra GMI bus controller Mirza Krak
@ 2016-08-24 13:37 ` Mirza Krak
0 siblings, 0 replies; 2+ messages in thread
From: Mirza Krak @ 2016-08-24 13:37 UTC (permalink / raw)
To: swarren, thierry.reding, jonathanh
Cc: gnurou, linux, pdeschrijver, pgaikwad, mturquette, sboyd,
robh+dt, mark.rutland, devicetree, linux-tegra, linux-kernel,
linux-arm-kernel, linux-clk, Mirza Krak
From: Mirza Krak <mirza.krak@gmail.com>
Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which
is max rate.
Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
---
Changes in v2:
- no changes
drivers/clk/tegra/clk-tegra30.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 8e2db5e..67f1677 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1252,6 +1252,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
{ TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
{ TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
+ { TEGRA30_CLK_NOR, TEGRA30_CLK_PLL_P, 127000000, 0 },
{ TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 },
{ TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1 },
{ TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
--
2.1.4
^ permalink raw reply [flat|nested] 2+ messages in thread
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[not found] <1472569320.5703.23.camel@toradex.com>
2016-08-31 7:17 ` [PATCH v2 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table Marcel Ziswiler
2016-08-24 13:37 [PATCH v2 0/6] Add support for Tegra GMI bus controller Mirza Krak
2016-08-24 13:37 ` [PATCH v2 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table Mirza Krak
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