From: "Fenghua Yu" <fenghua.yu@intel.com>
To: "Thomas Gleixner" <tglx@linutronix.de>
Cc: "H. Peter Anvin" <h.peter.anvin@intel.com>,
"Ingo Molnar" <mingo@elte.hu>, "Tony Luck" <tony.luck@intel.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Stephane Eranian" <eranian@google.com>,
"Borislav Petkov" <bp@suse.de>,
"Dave Hansen" <dave.hansen@intel.com>,
"Nilay Vaish" <nilayvaish@gmail.com>, "Shaohua Li" <shli@fb.com>,
"David Carrillo-Cisneros" <davidcc@google.com>,
"Ravi V Shankar" <ravi.v.shankar@intel.com>,
"Sai Prakhya" <sai.praneeth.prakhya@intel.com>,
"Vikas Shivappa" <vikas.shivappa@linux.intel.com>,
"linux-kernel" <linux-kernel@vger.kernel.org>,
"x86" <x86@kernel.org>, "Fenghua Yu" <fenghua.yu@intel.com>
Subject: [PATCH v4 01/18] Documentation, ABI: Add a document entry for cache id
Date: Fri, 14 Oct 2016 19:12:11 -0700 [thread overview]
Message-ID: <1476497548-11169-2-git-send-email-fenghua.yu@intel.com> (raw)
In-Reply-To: <1476497548-11169-1-git-send-email-fenghua.yu@intel.com>
From: Fenghua Yu <fenghua.yu@intel.com>
Add an ABI document entry for /sys/devices/system/cpu/cpu*/cache/index*/id.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
---
Documentation/ABI/testing/sysfs-devices-system-cpu | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
index 4987417..b1c3d69 100644
--- a/Documentation/ABI/testing/sysfs-devices-system-cpu
+++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
@@ -272,6 +272,22 @@ Description: Parameters for the CPU cache attributes
the modified cache line is written to main
memory only when it is replaced
+
+What: /sys/devices/system/cpu/cpu*/cache/index*/id
+Date: September 2016
+Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
+Description: Cache id
+
+ The id provides a unique name for a specific instance of
+ a cache of a particular type. E.g. there may be a level
+ 3 unified cache on each socket in a server and we may
+ assign them ids 0, 1, 2, ...
+
+ Note that id value may not be contiguous. E.g. level 1
+ caches typically exist per core, but there may not be a
+ power of two cores on a socket, so these caches may be
+ numbered 0, 1, 2, 3, 4, 5, 8, 9, 10, ...
+
What: /sys/devices/system/cpu/cpuX/cpufreq/throttle_stats
/sys/devices/system/cpu/cpuX/cpufreq/throttle_stats/turbo_stat
/sys/devices/system/cpu/cpuX/cpufreq/throttle_stats/sub_turbo_stat
--
2.5.0
next prev parent reply other threads:[~2016-10-14 23:09 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-15 2:12 [PATCH v4 00/18] Intel Cache Allocation Technology Fenghua Yu
2016-10-15 2:12 ` Fenghua Yu [this message]
2016-10-17 10:31 ` [PATCH v4 01/18] Documentation, ABI: Add a document entry for cache id Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 02/18] cacheinfo: Introduce " Fenghua Yu
2016-10-17 10:32 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 03/18] x86, intel_cacheinfo: Enable cache id in x86 Fenghua Yu
2016-10-17 10:48 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 04/18] x86/intel_rdt: Feature discovery Fenghua Yu
2016-10-15 2:12 ` [PATCH v4 05/18] Documentation, x86: Documentation for Intel resource allocation user interface Fenghua Yu
2016-10-15 2:12 ` [PATCH v4 06/18] x86/intel_rdt: Add CONFIG, Makefile, and basic initialization Fenghua Yu
2016-10-17 10:57 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 07/18] x86/intel_rdt: Add Haswell feature discovery Fenghua Yu
2016-10-17 11:03 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID Fenghua Yu
2016-10-17 13:45 ` Thomas Gleixner
2016-10-17 18:06 ` Fenghua Yu
2016-10-17 16:35 ` Luck, Tony
2016-10-17 16:43 ` Yu, Fenghua
2016-10-17 20:20 ` Luck, Tony
2016-10-17 16:54 ` Thomas Gleixner
2016-10-17 16:53 ` Thomas Gleixner
2016-10-17 17:02 ` Thomas Gleixner
2016-10-17 21:22 ` Fenghua Yu
2016-10-15 2:12 ` [PATCH v4 09/18] x86/cqm: Move PQR_ASSOC management code into generic code used by both CQM and CAT Fenghua Yu
2016-10-15 2:12 ` [PATCH v4 10/18] x86/intel_rdt: Build structures for each resource based on cache topology Fenghua Yu
2016-10-17 14:44 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 11/18] x86/intel_rdt: Add basic resctrl filesystem support Fenghua Yu
2016-10-17 19:35 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 12/18] x86/intel_rdt: Add "info" files to resctrl file system Fenghua Yu
2016-10-17 19:46 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 13/18] x86/intel_rdt: Add mkdir " Fenghua Yu
2016-10-17 21:14 ` Thomas Gleixner
2016-10-17 21:50 ` Luck, Tony
2016-10-17 22:52 ` Thomas Gleixner
2016-10-17 23:00 ` Luck, Tony
2016-10-17 23:03 ` Thomas Gleixner
2016-10-17 23:10 ` Luck, Tony
2016-10-17 23:25 ` Thomas Gleixner
2016-10-18 1:18 ` Fenghua Yu
2016-10-17 23:20 ` Thomas Gleixner
2016-10-17 23:37 ` Luck, Tony
2016-10-18 2:56 ` Fenghua Yu
2016-10-18 10:44 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 14/18] x86/intel_rdt: Add cpus file Fenghua Yu
2016-10-17 21:27 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 15/18] x86/intel_rdt: Add tasks files Fenghua Yu
2016-10-17 22:01 ` Thomas Gleixner
2016-10-17 22:17 ` Luck, Tony
2016-10-15 2:12 ` [PATCH v4 16/18] x86/intel_rdt: Add schemata file Fenghua Yu
2016-10-17 22:35 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 17/18] x86/intel_rdt: Add scheduler hook Fenghua Yu
2016-10-15 2:12 ` [PATCH v4 18/18] MAINTAINERS: Add maintainer for Intel RDT resource allocation Fenghua Yu
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