From: Thomas Gleixner <tglx@linutronix.de>
To: Fenghua Yu <fenghua.yu@intel.com>
Cc: "H. Peter Anvin" <h.peter.anvin@intel.com>,
Ingo Molnar <mingo@elte.hu>, Tony Luck <tony.luck@intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Stephane Eranian <eranian@google.com>,
Borislav Petkov <bp@suse.de>, Dave Hansen <dave.hansen@intel.com>,
Nilay Vaish <nilayvaish@gmail.com>, Shaohua Li <shli@fb.com>,
David Carrillo-Cisneros <davidcc@google.com>,
Ravi V Shankar <ravi.v.shankar@intel.com>,
Sai Prakhya <sai.praneeth.prakhya@intel.com>,
Vikas Shivappa <vikas.shivappa@linux.intel.com>,
linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: Re: [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID
Date: Mon, 17 Oct 2016 15:45:32 +0200 (CEST) [thread overview]
Message-ID: <alpine.DEB.2.20.1610171525390.9580@nanos> (raw)
In-Reply-To: <1476497548-11169-9-git-send-email-fenghua.yu@intel.com>
On Fri, 14 Oct 2016, Fenghua Yu wrote:
> +/**
> + * struct rdt_resource - attributes of an RDT resource
> + * @enabled: Is this feature enabled on this machine
> + * @name: Name to use in "schemata" file
> + * @max_closid: Maximum number of CLOSIDs supported
> + * @num_closid: Current number of CLOSIDs available
> + * @max_cbm: Largest Cache Bit Mask allowed
> + * @min_cbm_bits: Minimum number of bits to be set in a cache
That should be 'number of consecutive bits', right?
> + * bit mask
> + * @domains: All domains for this resource
> + * @num_domains: Number of domains active
> + * @msr_base: Base MSR address for CBMs
> + * @cdp_capable: Code/Data Prioritization available
> + * @cdp_enabled: Code/Data Prioritization enabled
I wonder whether this is the proper abstraction level. We might as well do
the following:
rdtresources[] = {
{
.name = "L3",
},
{
.name = "L3Data",
},
{
.name = "L3Code",
},
and enable either L3 or L3Data+L3Code. Not sure if that makes things
simpler, but it's definitely worth a thought or two.
> +#define for_each_rdt_resource(r) \
> + for (r = rdt_resources_all; r->name; r++) \
> + if (r->enabled)
So the resource array must be NULL terminated, right? You might as well use
r < rdt_resources_all + ARRAY_SIZE(rdt_resources_all)
as the loop condition. So you avoid the NULL termination.
> +
> +#define IA32_L3_CBM_BASE 0xc90
> +extern struct rdt_resource rdt_resources_all[];
Please visually split this. CBM_BASE has nothing to do with the resource
array.
> +#define domain_init(name) LIST_HEAD_INIT(rdt_resources_all[name].domains)
name is really misleading here. Please use id and make this an inline
function.
> +struct rdt_resource rdt_resources_all[] = {
> static inline bool get_rdt_resources(void)
> {
> + struct rdt_resource *r;
> bool ret = false;
>
> if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
> @@ -74,20 +105,53 @@ static inline bool get_rdt_resources(void)
>
> if (!boot_cpu_has(X86_FEATURE_RDT_A))
> return false;
> - if (boot_cpu_has(X86_FEATURE_CAT_L3))
> + if (boot_cpu_has(X86_FEATURE_CAT_L3)) {
> + union cpuid_0x10_1_eax eax;
> + union cpuid_0x10_1_edx edx;
> + u32 ebx, ecx;
> +
> + r = &rdt_resources_all[RDT_RESOURCE_L3];
> + cpuid_count(0x00000010, 1, &eax.full, &ebx, &ecx, &edx.full);
> + r->max_closid = edx.split.cos_max + 1;
> + r->num_closid = r->max_closid;
> + r->cbm_len = eax.split.cbm_len + 1;
> + r->max_cbm = BIT_MASK(eax.split.cbm_len + 1) - 1;
> + if (boot_cpu_has(X86_FEATURE_CDP_L3))
> + r->cdp_capable = true;
> + r->enabled = true;
> +
> ret = true;
> + }
> + if (boot_cpu_has(X86_FEATURE_CAT_L2)) {
> + union cpuid_0x10_1_eax eax;
> + union cpuid_0x10_1_edx edx;
> + u32 ebx, ecx;
> +
> + /* CPUID 0x10.2 fields are same format at 0x10.1 */
> + r = &rdt_resources_all[RDT_RESOURCE_L2];
> + cpuid_count(0x00000010, 2, &eax.full, &ebx, &ecx, &edx.full);
> + r->max_closid = edx.split.cos_max + 1;
> + r->num_closid = r->max_closid;
> + r->cbm_len = eax.split.cbm_len + 1;
> + r->max_cbm = BIT_MASK(eax.split.cbm_len + 1) - 1;
> + r->enabled = true;
Copy and paste is a wonderful thing, right?
static void rdt_get_config(int idx, struct rdt_resource *r)
{
union cpuid_0x10_1_eax eax;
union cpuid_0x10_1_edx edx;
u32 ebx, ecx;
cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full);
r->max_closid = edx.split.cos_max + 1;
r->num_closid = r->max_closid;
r->cbm_len = eax.split.cbm_len + 1;
r->max_cbm = BIT_MASK(eax.split.cbm_len + 1) - 1;
r->enabled = true;
}
and and the call site:
if (boot_cpu_has(X86_FEATURE_CAT_L3)) {
rdt_get_config(1, &rdt_resources_all[RDT_RESOURCE_L3]);
if (boot_cpu_has(X86_FEATURE_CDP_L3))
r->cdp_capable = true;
ret = true;
}
if (boot_cpu_has(X86_FEATURE_CAT_L2)) {
rdt_get_config(2, &rdt_resources_all[RDT_RESOURCE_L2]);
ret = true;
}
Hmm?
> + for_each_rdt_resource(r)
> + pr_info("Intel RDT %s allocation %s detected\n", r->name,
> + r->cdp_capable ? " (with CDP)" : "");
This want's curly braces around the loop.
Thanks,
tglx
next prev parent reply other threads:[~2016-10-17 13:48 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-15 2:12 [PATCH v4 00/18] Intel Cache Allocation Technology Fenghua Yu
2016-10-15 2:12 ` [PATCH v4 01/18] Documentation, ABI: Add a document entry for cache id Fenghua Yu
2016-10-17 10:31 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 02/18] cacheinfo: Introduce " Fenghua Yu
2016-10-17 10:32 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 03/18] x86, intel_cacheinfo: Enable cache id in x86 Fenghua Yu
2016-10-17 10:48 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 04/18] x86/intel_rdt: Feature discovery Fenghua Yu
2016-10-15 2:12 ` [PATCH v4 05/18] Documentation, x86: Documentation for Intel resource allocation user interface Fenghua Yu
2016-10-15 2:12 ` [PATCH v4 06/18] x86/intel_rdt: Add CONFIG, Makefile, and basic initialization Fenghua Yu
2016-10-17 10:57 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 07/18] x86/intel_rdt: Add Haswell feature discovery Fenghua Yu
2016-10-17 11:03 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID Fenghua Yu
2016-10-17 13:45 ` Thomas Gleixner [this message]
2016-10-17 18:06 ` Fenghua Yu
2016-10-17 16:35 ` Luck, Tony
2016-10-17 16:43 ` Yu, Fenghua
2016-10-17 20:20 ` Luck, Tony
2016-10-17 16:54 ` Thomas Gleixner
2016-10-17 16:53 ` Thomas Gleixner
2016-10-17 17:02 ` Thomas Gleixner
2016-10-17 21:22 ` Fenghua Yu
2016-10-15 2:12 ` [PATCH v4 09/18] x86/cqm: Move PQR_ASSOC management code into generic code used by both CQM and CAT Fenghua Yu
2016-10-15 2:12 ` [PATCH v4 10/18] x86/intel_rdt: Build structures for each resource based on cache topology Fenghua Yu
2016-10-17 14:44 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 11/18] x86/intel_rdt: Add basic resctrl filesystem support Fenghua Yu
2016-10-17 19:35 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 12/18] x86/intel_rdt: Add "info" files to resctrl file system Fenghua Yu
2016-10-17 19:46 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 13/18] x86/intel_rdt: Add mkdir " Fenghua Yu
2016-10-17 21:14 ` Thomas Gleixner
2016-10-17 21:50 ` Luck, Tony
2016-10-17 22:52 ` Thomas Gleixner
2016-10-17 23:00 ` Luck, Tony
2016-10-17 23:03 ` Thomas Gleixner
2016-10-17 23:10 ` Luck, Tony
2016-10-17 23:25 ` Thomas Gleixner
2016-10-18 1:18 ` Fenghua Yu
2016-10-17 23:20 ` Thomas Gleixner
2016-10-17 23:37 ` Luck, Tony
2016-10-18 2:56 ` Fenghua Yu
2016-10-18 10:44 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 14/18] x86/intel_rdt: Add cpus file Fenghua Yu
2016-10-17 21:27 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 15/18] x86/intel_rdt: Add tasks files Fenghua Yu
2016-10-17 22:01 ` Thomas Gleixner
2016-10-17 22:17 ` Luck, Tony
2016-10-15 2:12 ` [PATCH v4 16/18] x86/intel_rdt: Add schemata file Fenghua Yu
2016-10-17 22:35 ` Thomas Gleixner
2016-10-15 2:12 ` [PATCH v4 17/18] x86/intel_rdt: Add scheduler hook Fenghua Yu
2016-10-15 2:12 ` [PATCH v4 18/18] MAINTAINERS: Add maintainer for Intel RDT resource allocation Fenghua Yu
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