From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org,
mike.leach@linaro.org, Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v5 13/19] coresight tmc: Detect support for scatter gather
Date: Thu, 20 Jul 2017 11:17:23 +0100 [thread overview]
Message-ID: <1500545849-23724-14-git-send-email-suzuki.poulose@arm.com> (raw)
In-Reply-To: <1500545849-23724-1-git-send-email-suzuki.poulose@arm.com>
The SG unit in the TMC has been removed in Coresight SoC-600.
This is however advertised by DEVID:Bit 24 = 0b1. On the
previous generation, the bit is RES0, hence we can rely on the
DEVID to detect the support.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
drivers/hwtracing/coresight/coresight-tmc.c | 2 ++
drivers/hwtracing/coresight/coresight-tmc.h | 5 +++++
2 files changed, 7 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 4e7cd9a..6d9b8e3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -306,6 +306,8 @@ static int tmc_etr_setup_caps(struct tmc_drvdata *drvdata,
/* Set the unadvertised capabilities */
tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
+ if (!(devid & TMC_DEVID_NOSCAT))
+ tmc_etr_set_cap(drvdata, TMC_ETR_SG);
/*
* ETR configuration uses a 40-bit AXI master in place of
* the embedded SRAM of ETB/ETF.
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 7b20863..23dfbf3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -70,6 +70,8 @@
#define TMC_FFCR_STOP_ON_FLUSH BIT(12)
+#define TMC_DEVID_NOSCAT BIT(24)
+
enum tmc_config_type {
TMC_CONFIG_TYPE_ETB,
TMC_CONFIG_TYPE_ETR,
@@ -89,6 +91,9 @@ enum tmc_mem_intf_width {
TMC_MEM_INTF_WIDTH_256BITS = 8,
};
+/* TMC ETR Capability bit definitions */
+#define TMC_ETR_SG (0x1U << 0)
+
/**
* struct tmc_drvdata - specifics associated to an TMC component
* @base: memory mapped base address for this component.
--
2.7.5
next prev parent reply other threads:[~2017-07-20 10:18 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-20 10:17 [PATCH v5 00/19] coresight: Support for ARM Coresight SoC-600 Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 01/19] coresight replicator: Cleanup programmable replicator naming Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 02/19] arm64: juno: dts: Use the new coresight replicator string Suzuki K Poulose
2017-07-20 12:57 ` Liviu Dudau
2017-07-27 11:23 ` Sudeep Holla
2017-07-20 10:17 ` [PATCH v5 03/19] arm: qcom-msm8974: dts: Update coresight replicator Suzuki K Poulose
2017-07-27 11:17 ` Suzuki K Poulose
2017-07-27 21:01 ` Andy Gross
2017-07-20 10:17 ` [PATCH v5 04/19] arm64: qcom-msm8916: " Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 05/19] coresight: Extend the PIDR mask to cover relevant bits in PIDR2 Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 06/19] coresight: Add support for reading 64bit registers Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 07/19] coresight: Use the new helper for defining registers Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 08/19] coresight tmc: Add helpers for accessing 64bit registers Suzuki K Poulose
2017-07-24 17:11 ` Mathieu Poirier
2017-07-25 9:29 ` Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 09/19] coresight tmc: Expose DBA and AXICTL Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 10/19] coresight replicator: Expose replicator management registers Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 11/19] coresight tmc: Handle configuration types properly Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 12/19] coresight tmc etr: Add capabilitiy information Suzuki K Poulose
2017-07-20 10:17 ` Suzuki K Poulose [this message]
2017-07-20 10:17 ` [PATCH v5 14/19] coresight tmc etr: Detect address width at runtime Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 15/19] coresight tmc etr: Cleanup AXICTL register handling Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 16/19] coresigh tmc etr: Setup AXI cache encoding for read transfers Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 17/19] coresight tmc: Support for save-restore in ETR Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 18/19] coresight tmc: Add support for Coresight SoC 600 TMC Suzuki K Poulose
2017-07-24 17:12 ` Mathieu Poirier
2017-07-25 9:35 ` Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 19/19] coresight: Add support for Coresight SoC 600 components Suzuki K Poulose
2017-07-24 17:15 ` [PATCH v5 00/19] coresight: Support for ARM Coresight SoC-600 Mathieu Poirier
2017-07-25 9:40 ` Suzuki K Poulose
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