mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: Suzuki K Poulose <Suzuki.Poulose@arm.com>
To: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: "linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Mike Leach <mike.leach@linaro.org>
Subject: Re: [PATCH v5 00/19] coresight: Support for ARM Coresight SoC-600
Date: Tue, 25 Jul 2017 10:40:14 +0100	[thread overview]
Message-ID: <43a8483f-4afe-b9c8-f19a-c7b49350f004@arm.com> (raw)
In-Reply-To: <CANLsYkxGey6K=ybLnzNGj6utvwJXn=c+WXryr0YB6uEqcT-zmQ@mail.gmail.com>

On 24/07/17 18:15, Mathieu Poirier wrote:
> On 20 July 2017 at 04:17, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>> This series adds support for ARM Coresight SoC-600 IP, which implements
>> Coresight V3 architecture. It also does some clean up of the replicator
>> driver namings used in the driver to prevent confusions to the user.
>>
>> The SoC-600 comes with an improved TMC which supports new features,
>> including Save-Restore, Software FIFO2 mode (for streaming the trace
>> data over functional I/O like USB/PCI), and other changes AXICTL settings.
>>
>> This series supports Save-Restore feature of the new ETR by reusing
>> the driver to perform additional setups required in case we are dealing
>> with an IP which supports it. Towards this we keep track of the
>> capabilities of the given TMC ETR. Some of the features are advertised
>> via DEVID register (address width, scatter gather support), while some
>> are not (save-restore). So we attach a static capability mask with the
>> device PID for the unadvertised features and detect the rest at device
>> probe. The driver now detects the AXI address width if advertised via
>> DEVID.
>>
>> Tested on Juno (with Coresight SoC 400) and an FPGA based system
>> for SoC 600.
>
> Good day,
>
> Other than the two remarks I'm good with this set.  Since going for
> another iteration is time consuming for both of us I can make the
> modifications on my side - just let me know.

Mathieu,

Yes, I am happy with that. Thank you for the offer, it does save a lot
of time !

Cheers
Suzuki

      reply	other threads:[~2017-07-25  9:40 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-20 10:17 Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 01/19] coresight replicator: Cleanup programmable replicator naming Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 02/19] arm64: juno: dts: Use the new coresight replicator string Suzuki K Poulose
2017-07-20 12:57   ` Liviu Dudau
2017-07-27 11:23     ` Sudeep Holla
2017-07-20 10:17 ` [PATCH v5 03/19] arm: qcom-msm8974: dts: Update coresight replicator Suzuki K Poulose
2017-07-27 11:17   ` Suzuki K Poulose
2017-07-27 21:01     ` Andy Gross
2017-07-20 10:17 ` [PATCH v5 04/19] arm64: qcom-msm8916: " Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 05/19] coresight: Extend the PIDR mask to cover relevant bits in PIDR2 Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 06/19] coresight: Add support for reading 64bit registers Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 07/19] coresight: Use the new helper for defining registers Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 08/19] coresight tmc: Add helpers for accessing 64bit registers Suzuki K Poulose
2017-07-24 17:11   ` Mathieu Poirier
2017-07-25  9:29     ` Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 09/19] coresight tmc: Expose DBA and AXICTL Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 10/19] coresight replicator: Expose replicator management registers Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 11/19] coresight tmc: Handle configuration types properly Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 12/19] coresight tmc etr: Add capabilitiy information Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 13/19] coresight tmc: Detect support for scatter gather Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 14/19] coresight tmc etr: Detect address width at runtime Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 15/19] coresight tmc etr: Cleanup AXICTL register handling Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 16/19] coresigh tmc etr: Setup AXI cache encoding for read transfers Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 17/19] coresight tmc: Support for save-restore in ETR Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 18/19] coresight tmc: Add support for Coresight SoC 600 TMC Suzuki K Poulose
2017-07-24 17:12   ` Mathieu Poirier
2017-07-25  9:35     ` Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 19/19] coresight: Add support for Coresight SoC 600 components Suzuki K Poulose
2017-07-24 17:15 ` [PATCH v5 00/19] coresight: Support for ARM Coresight SoC-600 Mathieu Poirier
2017-07-25  9:40   ` Suzuki K Poulose [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=43a8483f-4afe-b9c8-f19a-c7b49350f004@arm.com \
    --to=suzuki.poulose@arm.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mathieu.poirier@linaro.org \
    --cc=mike.leach@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®