From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org,
mike.leach@linaro.org, Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v5 15/19] coresight tmc etr: Cleanup AXICTL register handling
Date: Thu, 20 Jul 2017 11:17:25 +0100 [thread overview]
Message-ID: <1500545849-23724-16-git-send-email-suzuki.poulose@arm.com> (raw)
In-Reply-To: <1500545849-23724-1-git-send-email-suzuki.poulose@arm.com>
This patch cleans up how we setup the AXICTL register on
TMC ETR. At the moment we don't set the CacheCtrl bits, which
drives the arcache and awcache bits on AXI bus specifying the
cacheablitiy. Set this to Write-back Read and Write-allocate.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 +++-------
drivers/hwtracing/coresight/coresight-tmc.h | 17 ++++++++++++++++-
2 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 9c39c89..880b535 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -36,13 +36,9 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
axictl = readl_relaxed(drvdata->base + TMC_AXICTL);
- axictl |= TMC_AXICTL_WR_BURST_16;
- writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
- axictl &= ~TMC_AXICTL_SCT_GAT_MODE;
- writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
- axictl = (axictl &
- ~(TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1)) |
- TMC_AXICTL_PROT_CTL_B1;
+ axictl &= ~TMC_AXICTL_CLEAR_MASK;
+ axictl |= (TMC_AXICTL_PROT_CTL_B1 | TMC_AXICTL_WR_BURST_16);
+ axictl |= TMC_AXICTL_AXCACHE_OS;
writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
tmc_write_dba(drvdata, drvdata->paddr);
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 3e94b4b..a532972 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -55,11 +55,26 @@
#define TMC_STS_TMCREADY_BIT 2
#define TMC_STS_FULL BIT(0)
#define TMC_STS_TRIGGERED BIT(1)
-/* TMC_AXICTL - 0x110 */
+/*
+ * TMC_AXICTL - 0x110
+ *
+ * TMC AXICTL format for SoC-400
+ * Bits [0-1] : ProtCtrlBit0-1
+ * Bits [2-5] : CacheCtrlBits 0-3 (AxCACHE)
+ * Bit 6 : Reserved
+ * Bit 7 : ScatterGatherMode
+ * Bits [8-11] : WrBurstLen
+ * Bits [12-31] : Reserved.
+ */
+#define TMC_AXICTL_CLEAR_MASK 0xfbf
+
#define TMC_AXICTL_PROT_CTL_B0 BIT(0)
#define TMC_AXICTL_PROT_CTL_B1 BIT(1)
#define TMC_AXICTL_SCT_GAT_MODE BIT(7)
#define TMC_AXICTL_WR_BURST_16 0xF00
+/* Write-back Read and Write-allocate */
+#define TMC_AXICTL_AXCACHE_OS (0xf << 2)
+
/* TMC_FFCR - 0x304 */
#define TMC_FFCR_FLUSHMAN_BIT 6
#define TMC_FFCR_EN_FMT BIT(0)
--
2.7.5
next prev parent reply other threads:[~2017-07-20 10:19 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-20 10:17 [PATCH v5 00/19] coresight: Support for ARM Coresight SoC-600 Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 01/19] coresight replicator: Cleanup programmable replicator naming Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 02/19] arm64: juno: dts: Use the new coresight replicator string Suzuki K Poulose
2017-07-20 12:57 ` Liviu Dudau
2017-07-27 11:23 ` Sudeep Holla
2017-07-20 10:17 ` [PATCH v5 03/19] arm: qcom-msm8974: dts: Update coresight replicator Suzuki K Poulose
2017-07-27 11:17 ` Suzuki K Poulose
2017-07-27 21:01 ` Andy Gross
2017-07-20 10:17 ` [PATCH v5 04/19] arm64: qcom-msm8916: " Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 05/19] coresight: Extend the PIDR mask to cover relevant bits in PIDR2 Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 06/19] coresight: Add support for reading 64bit registers Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 07/19] coresight: Use the new helper for defining registers Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 08/19] coresight tmc: Add helpers for accessing 64bit registers Suzuki K Poulose
2017-07-24 17:11 ` Mathieu Poirier
2017-07-25 9:29 ` Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 09/19] coresight tmc: Expose DBA and AXICTL Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 10/19] coresight replicator: Expose replicator management registers Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 11/19] coresight tmc: Handle configuration types properly Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 12/19] coresight tmc etr: Add capabilitiy information Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 13/19] coresight tmc: Detect support for scatter gather Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 14/19] coresight tmc etr: Detect address width at runtime Suzuki K Poulose
2017-07-20 10:17 ` Suzuki K Poulose [this message]
2017-07-20 10:17 ` [PATCH v5 16/19] coresigh tmc etr: Setup AXI cache encoding for read transfers Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 17/19] coresight tmc: Support for save-restore in ETR Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 18/19] coresight tmc: Add support for Coresight SoC 600 TMC Suzuki K Poulose
2017-07-24 17:12 ` Mathieu Poirier
2017-07-25 9:35 ` Suzuki K Poulose
2017-07-20 10:17 ` [PATCH v5 19/19] coresight: Add support for Coresight SoC 600 components Suzuki K Poulose
2017-07-24 17:15 ` [PATCH v5 00/19] coresight: Support for ARM Coresight SoC-600 Mathieu Poirier
2017-07-25 9:40 ` Suzuki K Poulose
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