From: Tudor Ambarus <tudor.ambarus@microchip.com>
To: Michael Walle <michael@walle.cc>, <linux-mtd@lists.infradead.org>,
"Miquel Raynal" <miquel.raynal@bootlin.com>,
Mark Brown <broonie@kernel.org>, <linux-kernel@vger.kernel.org>,
Pratyush Yadav <p.yadav@ti.com>,
"Richard Weinberger" <richard@nod.at>,
<linux-spi@vger.kernel.org>,
Vignesh Raghavendra <vigneshr@ti.com>
Cc: Tudor Ambarus <tudor.ambarus@microchip.com>
Subject: (subset) Re: [PATCH v2 0/6] Avoid odd length/address read/writes in 8D-8D-8D mode.
Date: Thu, 23 Dec 2021 15:31:08 +0200 [thread overview]
Message-ID: <164026605398.210110.7825546754254895590.b4-ty@microchip.com> (raw)
In-Reply-To: <20210531181757.19458-1-p.yadav@ti.com>
On Mon, 31 May 2021 23:47:51 +0530, Pratyush Yadav wrote:
> On Octal DTR flashes like Micron Xcella or Cypress S28 family, reads or
> writes cannot start at an odd address in 8D-8D-8D mode. Neither can they
> be odd bytes long. Upper layers like filesystems don't know what mode
> the flash is in, and hence don't know the read/write address or length
> limitations. They might issue reads or writes that leave the flash in an
> error state. In fact, using UBIFS on top of the flash was how I first
> noticed this problem.
>
> [...]
Applied to spi-nor/next, thanks!
[1/6] mtd: spi-nor: core: use 2 data bytes for template ops
https://git.kernel.org/mtd/c/0d051a49829a
[2/6] mtd: spi-nor: spansion: write 2 bytes when disabling Octal DTR mode
https://git.kernel.org/mtd/c/63017068a6d9
[3/6] mtd: spi-nor: micron-st: write 2 bytes when disabling Octal DTR mode
https://git.kernel.org/mtd/c/9de3cb1cc95b
Best regards,
--
Tudor Ambarus <tudor.ambarus@microchip.com>
prev parent reply other threads:[~2021-12-23 13:31 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-31 18:17 Pratyush Yadav
2021-05-31 18:17 ` [PATCH v2 1/6] mtd: spi-nor: core: use 2 data bytes for template ops Pratyush Yadav
2021-06-01 12:36 ` Michael Walle
2021-05-31 18:17 ` [PATCH v2 2/6] mtd: spi-nor: spansion: write 2 bytes when disabling Octal DTR mode Pratyush Yadav
2021-06-01 12:47 ` Michael Walle
2021-06-02 7:42 ` Pratyush Yadav
2021-12-23 13:06 ` Tudor.Ambarus
2021-12-23 13:11 ` Tudor.Ambarus
2021-12-23 13:24 ` Tudor.Ambarus
2021-05-31 18:17 ` [PATCH v2 3/6] mtd: spi-nor: micron-st: " Pratyush Yadav
2021-05-31 18:17 ` [PATCH v2 4/6] spi: spi-mem: reject partial cycle transfers in 8D-8D-8D mode Pratyush Yadav
2021-12-23 11:43 ` Tudor.Ambarus
2021-12-23 11:47 ` Pratyush Yadav
2021-05-31 18:17 ` [PATCH v2 5/6] mtd: spi-nor: core: avoid odd length/address reads on " Pratyush Yadav
2021-12-23 12:42 ` Tudor.Ambarus
2021-05-31 18:17 ` [PATCH v2 6/6] mtd: spi-nor: core: avoid odd length/address writes in " Pratyush Yadav
2021-06-01 12:44 ` Michael Walle
2021-12-23 12:59 ` Tudor.Ambarus
2021-12-23 13:31 ` Tudor Ambarus [this message]
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