From: Michael Walle <michael@walle.cc>
To: Pratyush Yadav <p.yadav@ti.com>
Cc: Tudor Ambarus <tudor.ambarus@microchip.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Mark Brown <broonie@kernel.org>,
linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-spi@vger.kernel.org
Subject: Re: [PATCH v2 1/6] mtd: spi-nor: core: use 2 data bytes for template ops
Date: Tue, 01 Jun 2021 14:36:28 +0200 [thread overview]
Message-ID: <543350e0bc25f84a0ba9f464dcfa15bf@walle.cc> (raw)
In-Reply-To: <20210531181757.19458-2-p.yadav@ti.com>
Am 2021-05-31 20:17, schrieb Pratyush Yadav:
> The template ops used in spi_nor_spimem_check_pp() and
> spi_nor_spimem_check_readop() currently set the data phase to 1 byte
> long. This is problematic for 8D-8D-8D protocol where odd length data
> phase is invalid since one cycle transfers 2 bytes and odd number of
> bytes would mean half a cycle is left over. This could result in a
> controller rejecting the op as "not supported" even though it actually
> supports the protocol.
>
> Change the data length to 2 bytes in these templates. One might argue
> that this should only be done for 8D-8D-8D operations but when talking
> about these templates, there is no functional difference between one
> and
> two bytes, even in STR modes.
>
> Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> ---
Reviewed-by: Michael Walle <michael@walle.cc>
next prev parent reply other threads:[~2021-06-01 12:36 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-31 18:17 [PATCH v2 0/6] Avoid odd length/address read/writes in 8D-8D-8D mode Pratyush Yadav
2021-05-31 18:17 ` [PATCH v2 1/6] mtd: spi-nor: core: use 2 data bytes for template ops Pratyush Yadav
2021-06-01 12:36 ` Michael Walle [this message]
2021-05-31 18:17 ` [PATCH v2 2/6] mtd: spi-nor: spansion: write 2 bytes when disabling Octal DTR mode Pratyush Yadav
2021-06-01 12:47 ` Michael Walle
2021-06-02 7:42 ` Pratyush Yadav
2021-12-23 13:06 ` Tudor.Ambarus
2021-12-23 13:11 ` Tudor.Ambarus
2021-12-23 13:24 ` Tudor.Ambarus
2021-05-31 18:17 ` [PATCH v2 3/6] mtd: spi-nor: micron-st: " Pratyush Yadav
2021-05-31 18:17 ` [PATCH v2 4/6] spi: spi-mem: reject partial cycle transfers in 8D-8D-8D mode Pratyush Yadav
2021-12-23 11:43 ` Tudor.Ambarus
2021-12-23 11:47 ` Pratyush Yadav
2021-05-31 18:17 ` [PATCH v2 5/6] mtd: spi-nor: core: avoid odd length/address reads on " Pratyush Yadav
2021-12-23 12:42 ` Tudor.Ambarus
2021-05-31 18:17 ` [PATCH v2 6/6] mtd: spi-nor: core: avoid odd length/address writes in " Pratyush Yadav
2021-06-01 12:44 ` Michael Walle
2021-12-23 12:59 ` Tudor.Ambarus
2021-12-23 13:31 ` (subset) Re: [PATCH v2 0/6] Avoid odd length/address read/writes " Tudor Ambarus
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