[PATCH] spi: spi-geni-qcom: Correct CS_TOGGLE bit in SPI_TRANS_CFG

[PATCH] spi: spi-geni-qcom: Correct CS_TOGGLE bit in SPI_TRANS_CFG

[Vijaya Krishna Nivarthi]

The CS_TOGGLE bit when set is supposed to instruct FW to
toggle CS line between words. The driver with intent of
disabling this behaviour has been unsetting BIT(0). This has
not caused any trouble so far because the original BIT(1)
is untouched and BIT(0) likely wasn't being used.

Correct this to prevent a potential future bug.

Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
---
 drivers/spi/spi-geni-qcom.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index ba7be50..8a7d1c2 100644
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -35,7 +35,7 @@
 #define CS_DEMUX_OUTPUT_SEL	GENMASK(3, 0)
 
 #define SE_SPI_TRANS_CFG	0x25c
-#define CS_TOGGLE		BIT(0)
+#define CS_TOGGLE		BIT(1)
 
 #define SE_SPI_WORD_LEN		0x268
 #define WORD_LEN_MSK		GENMASK(9, 0)
-- 
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation.

Re: [PATCH] spi: spi-geni-qcom: Correct CS_TOGGLE bit in SPI_TRANS_CFG

[Konrad Dybcio]

On 4/25/23 09:42, Vijaya Krishna Nivarthi wrote:
> The CS_TOGGLE bit when set is supposed to instruct FW to
> toggle CS line between words. The driver with intent of
> disabling this behaviour has been unsetting BIT(0). This has
> not caused any trouble so far because the original BIT(1)
> is untouched and BIT(0) likely wasn't being used.
>
> Correct this to prevent a potential future bug.
>
> Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
> ---

Has this always been the case, or did the switch to BIT(1)
only occur on some recent platforms?

Konrad

>   drivers/spi/spi-geni-qcom.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
> index ba7be50..8a7d1c2 100644
> --- a/drivers/spi/spi-geni-qcom.c
> +++ b/drivers/spi/spi-geni-qcom.c
> @@ -35,7 +35,7 @@
>   #define CS_DEMUX_OUTPUT_SEL	GENMASK(3, 0)
>   
>   #define SE_SPI_TRANS_CFG	0x25c
> -#define CS_TOGGLE		BIT(0)
> +#define CS_TOGGLE		BIT(1)
>   
>   #define SE_SPI_WORD_LEN		0x268
>   #define WORD_LEN_MSK		GENMASK(9, 0)

Re: [PATCH] spi: spi-geni-qcom: Correct CS_TOGGLE bit in SPI_TRANS_CFG

[Vijaya Krishna Nivarthi]

On 4/25/2023 7:15 PM, Konrad Dybcio wrote:
>
> On 4/25/23 09:42, Vijaya Krishna Nivarthi wrote:
>> The CS_TOGGLE bit when set is supposed to instruct FW to
>> toggle CS line between words. The driver with intent of
>> disabling this behaviour has been unsetting BIT(0). This has
>> not caused any trouble so far because the original BIT(1)
>> is untouched and BIT(0) likely wasn't being used.
>>
>> Correct this to prevent a potential future bug.
>>
>> Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
>> ---
>
> Has this always been the case, or did the switch to BIT(1)
> only occur on some recent platforms?


Thank you very much for the review..

This has always been the case.

With intent of disabling CS_TOGGLE, currently, the driver is unsetting 
BIT(0), though it should have been BIT(1).

Yet no problem was encountered because

a) BIT(0) seems to be an unused bit

b) BIT(1) is probably already unset because its untouched

Further more, as Doug pointed we are mostly using GPIO for CS.


Testing with the change has not caused any regressions.


Thank you,

Vijay/



>
> Konrad
>
>>   drivers/spi/spi-geni-qcom.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
>> index ba7be50..8a7d1c2 100644
>> --- a/drivers/spi/spi-geni-qcom.c
>> +++ b/drivers/spi/spi-geni-qcom.c
>> @@ -35,7 +35,7 @@
>>   #define CS_DEMUX_OUTPUT_SEL    GENMASK(3, 0)
>>     #define SE_SPI_TRANS_CFG    0x25c
>> -#define CS_TOGGLE        BIT(0)
>> +#define CS_TOGGLE        BIT(1)
>>     #define SE_SPI_WORD_LEN        0x268
>>   #define WORD_LEN_MSK        GENMASK(9, 0)

Re: [PATCH] spi: spi-geni-qcom: Correct CS_TOGGLE bit in SPI_TRANS_CFG

[Konrad Dybcio]

On 1.05.2023 10:05, Vijaya Krishna Nivarthi wrote:
> On 4/25/2023 7:15 PM, Konrad Dybcio wrote:
>>
>> On 4/25/23 09:42, Vijaya Krishna Nivarthi wrote:
>>> The CS_TOGGLE bit when set is supposed to instruct FW to
>>> toggle CS line between words. The driver with intent of
>>> disabling this behaviour has been unsetting BIT(0). This has
>>> not caused any trouble so far because the original BIT(1)
>>> is untouched and BIT(0) likely wasn't being used.
>>>
>>> Correct this to prevent a potential future bug.
>>>
>>> Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
>>> ---
>>
>> Has this always been the case, or did the switch to BIT(1)
>> only occur on some recent platforms?
> 
> 
> Thank you very much for the review..
> 
> This has always been the case.
> 
> With intent of disabling CS_TOGGLE, currently, the driver is unsetting BIT(0), though it should have been BIT(1).
> 
> Yet no problem was encountered because
> 
> a) BIT(0) seems to be an unused bit
> 
> b) BIT(1) is probably already unset because its untouched
> 
> Further more, as Doug pointed we are mostly using GPIO for CS.
> 
> 
> Testing with the change has not caused any regressions.
Okay, with no deeper knowledge of the topic best I can give you is:

Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>


Konrad
> 
> 
> Thank you,
> 
> Vijay/
> 
> 
> 
>>
>> Konrad
>>
>>>   drivers/spi/spi-geni-qcom.c | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
>>> index ba7be50..8a7d1c2 100644
>>> --- a/drivers/spi/spi-geni-qcom.c
>>> +++ b/drivers/spi/spi-geni-qcom.c
>>> @@ -35,7 +35,7 @@
>>>   #define CS_DEMUX_OUTPUT_SEL    GENMASK(3, 0)
>>>     #define SE_SPI_TRANS_CFG    0x25c
>>> -#define CS_TOGGLE        BIT(0)
>>> +#define CS_TOGGLE        BIT(1)
>>>     #define SE_SPI_WORD_LEN        0x268
>>>   #define WORD_LEN_MSK        GENMASK(9, 0)

Re: [PATCH] spi: spi-geni-qcom: Correct CS_TOGGLE bit in SPI_TRANS_CFG

[Konrad Dybcio]

On 1.05.2023 14:43, Konrad Dybcio wrote:
> 
> 
> On 1.05.2023 10:05, Vijaya Krishna Nivarthi wrote:
>> On 4/25/2023 7:15 PM, Konrad Dybcio wrote:
>>>
>>> On 4/25/23 09:42, Vijaya Krishna Nivarthi wrote:
>>>> The CS_TOGGLE bit when set is supposed to instruct FW to
>>>> toggle CS line between words. The driver with intent of
>>>> disabling this behaviour has been unsetting BIT(0). This has
>>>> not caused any trouble so far because the original BIT(1)
>>>> is untouched and BIT(0) likely wasn't being used.
>>>>
>>>> Correct this to prevent a potential future bug.
>>>>
>>>> Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
>>>> ---
>>>
>>> Has this always been the case, or did the switch to BIT(1)
>>> only occur on some recent platforms?
>>
>>
>> Thank you very much for the review..
>>
>> This has always been the case.
>>
>> With intent of disabling CS_TOGGLE, currently, the driver is unsetting BIT(0), though it should have been BIT(1).
>>
>> Yet no problem was encountered because
>>
>> a) BIT(0) seems to be an unused bit
>>
>> b) BIT(1) is probably already unset because its untouched
>>
>> Further more, as Doug pointed we are mostly using GPIO for CS.
>>
>>
>> Testing with the change has not caused any regressions.
> Okay, with no deeper knowledge of the topic best I can give you is:
> 
> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> 
> 
Also, missing:

Fixes: 561de45f72bd ("spi: spi-geni-qcom: Add SPI driver support for GENI based QUP")

Konrad
> Konrad
>>
>>
>> Thank you,
>>
>> Vijay/
>>
>>
>>
>>>
>>> Konrad
>>>
>>>>   drivers/spi/spi-geni-qcom.c | 2 +-
>>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
>>>> index ba7be50..8a7d1c2 100644
>>>> --- a/drivers/spi/spi-geni-qcom.c
>>>> +++ b/drivers/spi/spi-geni-qcom.c
>>>> @@ -35,7 +35,7 @@
>>>>   #define CS_DEMUX_OUTPUT_SEL    GENMASK(3, 0)
>>>>     #define SE_SPI_TRANS_CFG    0x25c
>>>> -#define CS_TOGGLE        BIT(0)
>>>> +#define CS_TOGGLE        BIT(1)
>>>>     #define SE_SPI_WORD_LEN        0x268
>>>>   #define WORD_LEN_MSK        GENMASK(9, 0)

Re: [PATCH] spi: spi-geni-qcom: Correct CS_TOGGLE bit in SPI_TRANS_CFG

[Doug Anderson]

Hi,

On Tue, Apr 25, 2023 at 1:42 AM Vijaya Krishna Nivarthi
<quic_vnivarth@quicinc.com> wrote:
>
> The CS_TOGGLE bit when set is supposed to instruct FW to
> toggle CS line between words. The driver with intent of
> disabling this behaviour has been unsetting BIT(0). This has
> not caused any trouble so far because the original BIT(1)
> is untouched and BIT(0) likely wasn't being used.
>
> Correct this to prevent a potential future bug.
>
> Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
> ---
>  drivers/spi/spi-geni-qcom.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
> index ba7be50..8a7d1c2 100644
> --- a/drivers/spi/spi-geni-qcom.c
> +++ b/drivers/spi/spi-geni-qcom.c
> @@ -35,7 +35,7 @@
>  #define CS_DEMUX_OUTPUT_SEL    GENMASK(3, 0)
>
>  #define SE_SPI_TRANS_CFG       0x25c
> -#define CS_TOGGLE              BIT(0)
> +#define CS_TOGGLE              BIT(1)

Looks right to me from the datasheet I have access to. It's definitely
specified in an odd way on the datasheet, which lists bit 1 as this,
bit 2 and 3 as reserved, but bit 0 is absent. ...but seems like this
is really supposed to be 1.

I guess this never mattered because all we ever did was clear the bit
at init time and it must have already been cleared? ...and, of course,
on many Chromebooks we moved to just using a GPIO...

Fixes: 561de45f72bd ("spi: spi-geni-qcom: Add SPI driver support for
GENI based QUP")
Reviewed-by: Douglas Anderson <dianders@chromium.org>

Re: [PATCH] spi: spi-geni-qcom: Correct CS_TOGGLE bit in SPI_TRANS_CFG

[Mark Brown]

On Tue, 25 Apr 2023 14:12:08 +0530, Vijaya Krishna Nivarthi wrote:
> The CS_TOGGLE bit when set is supposed to instruct FW to
> toggle CS line between words. The driver with intent of
> disabling this behaviour has been unsetting BIT(0). This has
> not caused any trouble so far because the original BIT(1)
> is untouched and BIT(0) likely wasn't being used.
> 
> Correct this to prevent a potential future bug.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/1] spi: spi-geni-qcom: Correct CS_TOGGLE bit in SPI_TRANS_CFG
      commit: 5fd7c99ecf45c8ee8a9b1268f0ffc91cc6271da2

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark