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From: "tip-bot2 for Ahmed S. Darwish" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: "Ahmed S. Darwish" <darwi@linutronix.de>,
	Ingo Molnar <mingo@kernel.org>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	"H. Peter Anvin" <hpa@zytor.com>,
	x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: x86/cpu] <linux/sizes.h>: Cover all possible x86 CPU cache sizes
Date: Tue, 04 Mar 2025 10:26:14 -0000	[thread overview]
Message-ID: <174108397433.14745.2749101050747192686.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20250304085152.51092-31-darwi@linutronix.de>

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     4f2a0b765c9731d2fa94e209ee9ae0e96b280f17
Gitweb:        https://git.kernel.org/tip/4f2a0b765c9731d2fa94e209ee9ae0e96b280f17
Author:        Ahmed S. Darwish <darwi@linutronix.de>
AuthorDate:    Tue, 04 Mar 2025 09:51:41 +01:00
Committer:     Ingo Molnar <mingo@kernel.org>
CommitterDate: Tue, 04 Mar 2025 11:17:33 +01:00

<linux/sizes.h>: Cover all possible x86 CPU cache sizes

Add size macros for 24/192/384 Kilobytes and 3/6/12/18/24 Megabytes.

With that, the x86 subsystem can avoid locally defining its own macros
for CPU cache sizes.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Link: https://lore.kernel.org/r/20250304085152.51092-31-darwi@linutronix.de
---
 include/linux/sizes.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/include/linux/sizes.h b/include/linux/sizes.h
index c3a00b9..4903949 100644
--- a/include/linux/sizes.h
+++ b/include/linux/sizes.h
@@ -23,17 +23,25 @@
 #define SZ_4K				0x00001000
 #define SZ_8K				0x00002000
 #define SZ_16K				0x00004000
+#define SZ_24K				0x00006000
 #define SZ_32K				0x00008000
 #define SZ_64K				0x00010000
 #define SZ_128K				0x00020000
+#define SZ_192K				0x00030000
 #define SZ_256K				0x00040000
+#define SZ_384K				0x00060000
 #define SZ_512K				0x00080000
 
 #define SZ_1M				0x00100000
 #define SZ_2M				0x00200000
+#define SZ_3M				0x00300000
 #define SZ_4M				0x00400000
+#define SZ_6M				0x00600000
 #define SZ_8M				0x00800000
+#define SZ_12M				0x00c00000
 #define SZ_16M				0x01000000
+#define SZ_18M				0x01200000
+#define SZ_24M				0x01800000
 #define SZ_32M				0x02000000
 #define SZ_64M				0x04000000
 #define SZ_128M				0x08000000

  parent reply	other threads:[~2025-03-04 10:26 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-04  8:51 [PATCH v1 00/40] x86: Leaf 0x2 and leaf 0x4 refactorings Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 01/40] x86/cacheinfo: Validate cpuid leaf 0x2 EDX output Ahmed S. Darwish
2025-03-04  9:37   ` [tip: x86/urgent] x86/cacheinfo: Validate CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 02/40] x86/cpu: Validate cpuid " Ahmed S. Darwish
2025-03-04  9:37   ` [tip: x86/urgent] x86/cpu: Validate CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 03/40] x86/cpu: Properly parse leaf 0x2 TLB descriptor 0x63 Ahmed S. Darwish
2025-03-04  9:37   ` [tip: x86/urgent] x86/cpu: Properly parse CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 04/40] x86/cpuid: Include linux/build_bug.h Ahmed S. Darwish
2025-03-04  9:37   ` [tip: x86/cpu] x86/cpuid: Include <linux/build_bug.h> in <asm/cpuid.h> tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26   ` tip-bot2 for Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 05/40] x86/cpu: Remove unnecessary headers and reorder the rest Ahmed S. Darwish
2025-03-04  9:14   ` Ingo Molnar
2025-03-04  9:28     ` Ahmed S. Darwish
2025-03-04  9:37   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26   ` tip-bot2 for Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 06/40] x86/cpu: Use max() for leaf 0x2 TLB descriptors parsing Ahmed S. Darwish
2025-03-04  9:37   ` [tip: x86/cpu] x86/cpu: Use max() for CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26   ` tip-bot2 for Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 07/40] x86/cpu: Simplify TLB entry count storage Ahmed S. Darwish
2025-03-04  9:37   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26   ` tip-bot2 for Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 08/40] x86/cpu: Get rid of smp_store_cpu_info() indirection Ahmed S. Darwish
2025-03-04  9:37   ` [tip: x86/cpu] x86/cpu: Get rid of the " tip-bot2 for Thomas Gleixner
2025-03-04 10:26   ` tip-bot2 for Thomas Gleixner
2025-03-04  8:51 ` [PATCH v1 09/40] x86/cpu: Remove unused TLB strings Ahmed S. Darwish
2025-03-04  9:37   ` [tip: x86/cpu] " tip-bot2 for Thomas Gleixner
2025-03-04 10:26   ` tip-bot2 for Thomas Gleixner
2025-03-04  8:51 ` [PATCH v1 10/40] x86/cpu: Remove leaf 0x2 parsing loop and add helpers Ahmed S. Darwish
2025-03-04  9:26   ` Ingo Molnar
2025-03-05 16:01     ` Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 11/40] x86/cacheinfo: Remove the P4 trace leftovers for real Ahmed S. Darwish
2025-03-04  9:47   ` [tip: x86/cpu] " tip-bot2 for Thomas Gleixner
2025-03-04 10:26   ` tip-bot2 for Thomas Gleixner
2025-03-04  8:51 ` [PATCH v1 12/40] x86/cacheinfo: Remove unnecessary headers and reorder the rest Ahmed S. Darwish
2025-03-04  9:47   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26   ` tip-bot2 for Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 13/40] x86/cacheinfo: Use cpuid leaf 0x2 parsing helpers Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 14/40] x86/cacheinfo: Refactor leaf 0x2 cache descriptor lookup Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 15/40] x86/cacheinfo: Properly name amd_cpuid4()'s first parameter Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 16/40] x86/cacheinfo: Use proper name for cacheinfo instances Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 17/40] x86/cacheinfo: Constify _cpuid4_info_regs instances Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 18/40] x86/cacheinfo: Align ci_info_init() assignment expressions Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 19/40] x86/cacheinfo: Standardize _cpuid4_info_regs instance naming Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 20/40] x86: treewide: Introduce x86_vendor_amd_or_hygon() Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 21/40] x86/cacheinfo: Consolidate AMD/Hygon leaf 0x8000001d calls Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 22/40] x86/cacheinfo: Separate amd_northbridge from _cpuid4_info_regs Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 23/40] x86/cacheinfo: Move AMD cache_disable_0/1 handling to separate file Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 24/40] x86/cacheinfo: Use sysfs_emit() for sysfs attributes show() Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 25/40] x86/cacheinfo: Separate Intel and AMD leaf 0x4 code paths Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 26/40] x86/cacheinfo: Rename _cpuid4_info_regs to _cpuid4_info Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 27/40] x86/cacheinfo: Clarify type markers for leaf 0x2 cache descriptors Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 28/40] x86/cacheinfo: Use enums for cache descriptor types Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 29/40] x86/cpu: Use enums for TLB " Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 30/40] sizes.h: Cover all possible x86 cpu cache sizes Ahmed S. Darwish
2025-03-04  9:35   ` Ingo Molnar
2025-03-05 16:18     ` Ahmed S. Darwish
2025-03-04  9:47   ` [tip: x86/cpu] <linux/sizes.h>: Cover all possible x86 CPU " tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26   ` tip-bot2 for Ahmed S. Darwish [this message]
2025-03-04  8:51 ` [PATCH v1 31/40] x86/cpu: Consolidate CPUID leaf 0x2 tables Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 32/40] x86/cacheinfo: Use consolidated leaf 0x2 descriptor table Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 33/40] x86/cpu: " Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 34/40] x86/cacheinfo: Separate leaf 0x2 handling and post-processing logic Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 35/40] x86/cacheinfo: Separate intel leaf 0x4 handling Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 36/40] x86/cacheinfo: Extract out cache level topology ID calculation Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 37/40] x86/cacheinfo: Extract out cache self-snoop checks Ahmed S. Darwish
2025-03-04 10:38   ` Andrew Cooper
2025-03-05 18:40     ` Ahmed S. Darwish
2025-03-05 18:42       ` Andrew Cooper
2025-03-05 18:58         ` Ahmed S. Darwish
2025-03-05 19:01           ` Andrew Cooper
2025-03-04  8:51 ` [PATCH v1 38/40] x86/cacheinfo: Relocate leaf 0x4 cache_type mapping Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 39/40] x86/cacheinfo: Introduce amd_hygon_cpu_has_l3_cache() Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 40/40] x86/cacheinfo: Apply maintainer-tip coding style fixes Ahmed S. Darwish
2025-03-04  9:19 ` [PATCH v1 00/40] x86: Leaf 0x2 and leaf 0x4 refactorings Ingo Molnar
2025-03-04  9:38   ` Ingo Molnar
2025-03-05 17:36     ` Ahmed S. Darwish
2025-03-04  9:33 ` Ingo Molnar
2025-03-05 16:38   ` Ahmed S. Darwish

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