mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: "Ahmed S. Darwish" <darwi@linutronix.de>
To: Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@redhat.com>,
	Dave Hansen <dave.hansen@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	John Ogness <john.ogness@linutronix.de>,
	"H. Peter Anvin" <hpa@zytor.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	x86@kernel.org, x86-cpuid@lists.linux.dev,
	LKML <linux-kernel@vger.kernel.org>,
	"Ahmed S. Darwish" <darwi@linutronix.de>
Subject: [PATCH v1 03/40] x86/cpu: Properly parse leaf 0x2 TLB descriptor 0x63
Date: Tue,  4 Mar 2025 09:51:14 +0100	[thread overview]
Message-ID: <20250304085152.51092-4-darwi@linutronix.de> (raw)
In-Reply-To: <20250304085152.51092-1-darwi@linutronix.de>

cpuid leaf 0x2's one-byte TLB descriptors report the number of entries
for specific TLB types, among other properties.

Typically, each emitted descriptor implies the same number of entries
for its respective TLB type(s).  An emitted 0x63 descriptor is an
exception: it implies 4 data TLB entries for 1GB pages and 32 data TLB
entries for 2MB or 4MB pages.

For the TLB descriptors parsing code, the entry count for 1GB pages is
encoded at the intel_tlb_table[] mapping, but the 2MB/4MB entry count is
totally ignored.

Update leaf 0x2's parsing logic 0x2 to account for 32 data TLB entries
for 2MB/4MB pages implied by the 0x63 descriptor.

Fixes: e0ba94f14f74 ("x86/tlb_info: get last level TLB entry number of CPU")
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/intel.c | 50 +++++++++++++++++++++++++------------
 1 file changed, 34 insertions(+), 16 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 2a3716afee63..134368a3f4b1 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -635,26 +635,37 @@ static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 }
 #endif
 
-#define TLB_INST_4K	0x01
-#define TLB_INST_4M	0x02
-#define TLB_INST_2M_4M	0x03
+#define TLB_INST_4K		0x01
+#define TLB_INST_4M		0x02
+#define TLB_INST_2M_4M		0x03
 
-#define TLB_INST_ALL	0x05
-#define TLB_INST_1G	0x06
+#define TLB_INST_ALL		0x05
+#define TLB_INST_1G		0x06
 
-#define TLB_DATA_4K	0x11
-#define TLB_DATA_4M	0x12
-#define TLB_DATA_2M_4M	0x13
-#define TLB_DATA_4K_4M	0x14
+#define TLB_DATA_4K		0x11
+#define TLB_DATA_4M		0x12
+#define TLB_DATA_2M_4M		0x13
+#define TLB_DATA_4K_4M		0x14
 
-#define TLB_DATA_1G	0x16
+#define TLB_DATA_1G		0x16
+#define TLB_DATA_1G_2M_4M	0x17
 
-#define TLB_DATA0_4K	0x21
-#define TLB_DATA0_4M	0x22
-#define TLB_DATA0_2M_4M	0x23
+#define TLB_DATA0_4K		0x21
+#define TLB_DATA0_4M		0x22
+#define TLB_DATA0_2M_4M		0x23
 
-#define STLB_4K		0x41
-#define STLB_4K_2M	0x42
+#define STLB_4K			0x41
+#define STLB_4K_2M		0x42
+
+/*
+ * All of leaf 0x2's one-byte TLB descriptors implies the same number of
+ * entries for their respective TLB types.  The 0x63 descriptor is an
+ * exception: it implies 4 dTLB entries for 1GB pages 32 dTLB entries
+ * for 2MB or 4MB pages.  Encode descriptor 0x63 dTLB entry count for
+ * 2MB/4MB pages here, as its count for dTLB 1GB pages is already at the
+ * intel_tlb_table[] mapping.
+ */
+#define TLB_0x63_2M_4M_ENTRIES	32
 
 static const struct _tlb_table intel_tlb_table[] = {
 	{ 0x01, TLB_INST_4K,		32,	" TLB_INST 4 KByte pages, 4-way set associative" },
@@ -676,7 +687,8 @@ static const struct _tlb_table intel_tlb_table[] = {
 	{ 0x5c, TLB_DATA_4K_4M,		128,	" TLB_DATA 4 KByte and 4 MByte pages" },
 	{ 0x5d, TLB_DATA_4K_4M,		256,	" TLB_DATA 4 KByte and 4 MByte pages" },
 	{ 0x61, TLB_INST_4K,		48,	" TLB_INST 4 KByte pages, full associative" },
-	{ 0x63, TLB_DATA_1G,		4,	" TLB_DATA 1 GByte pages, 4-way set associative" },
+	{ 0x63, TLB_DATA_1G_2M_4M,	4,	" TLB_DATA 1 GByte pages, 4-way set associative"
+						" (plus 32 entries TLB_DATA 2 MByte or 4 MByte pages, not encoded here)" },
 	{ 0x6b, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 8-way associative" },
 	{ 0x6c, TLB_DATA_2M_4M,		128,	" TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
 	{ 0x6d, TLB_DATA_1G,		16,	" TLB_DATA 1 GByte pages, fully associative" },
@@ -776,6 +788,12 @@ static void intel_tlb_lookup(const unsigned char desc)
 		if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
 			tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
 		break;
+	case TLB_DATA_1G_2M_4M:
+		if (tlb_lld_2m[ENTRIES] < TLB_0x63_2M_4M_ENTRIES)
+			tlb_lld_2m[ENTRIES] = TLB_0x63_2M_4M_ENTRIES;
+		if (tlb_lld_4m[ENTRIES] < TLB_0x63_2M_4M_ENTRIES)
+			tlb_lld_4m[ENTRIES] = TLB_0x63_2M_4M_ENTRIES;
+		fallthrough;
 	case TLB_DATA_1G:
 		if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
 			tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
-- 
2.48.1


  parent reply	other threads:[~2025-03-04  8:52 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-04  8:51 [PATCH v1 00/40] x86: Leaf 0x2 and leaf 0x4 refactorings Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 01/40] x86/cacheinfo: Validate cpuid leaf 0x2 EDX output Ahmed S. Darwish
2025-03-04  9:37   ` [tip: x86/urgent] x86/cacheinfo: Validate CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 02/40] x86/cpu: Validate cpuid " Ahmed S. Darwish
2025-03-04  9:37   ` [tip: x86/urgent] x86/cpu: Validate CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-04  8:51 ` Ahmed S. Darwish [this message]
2025-03-04  9:37   ` [tip: x86/urgent] x86/cpu: Properly parse CPUID leaf 0x2 TLB descriptor 0x63 tip-bot2 for Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 04/40] x86/cpuid: Include linux/build_bug.h Ahmed S. Darwish
2025-03-04  9:37   ` [tip: x86/cpu] x86/cpuid: Include <linux/build_bug.h> in <asm/cpuid.h> tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26   ` tip-bot2 for Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 05/40] x86/cpu: Remove unnecessary headers and reorder the rest Ahmed S. Darwish
2025-03-04  9:14   ` Ingo Molnar
2025-03-04  9:28     ` Ahmed S. Darwish
2025-03-04  9:37   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26   ` tip-bot2 for Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 06/40] x86/cpu: Use max() for leaf 0x2 TLB descriptors parsing Ahmed S. Darwish
2025-03-04  9:37   ` [tip: x86/cpu] x86/cpu: Use max() for CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26   ` tip-bot2 for Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 07/40] x86/cpu: Simplify TLB entry count storage Ahmed S. Darwish
2025-03-04  9:37   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26   ` tip-bot2 for Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 08/40] x86/cpu: Get rid of smp_store_cpu_info() indirection Ahmed S. Darwish
2025-03-04  9:37   ` [tip: x86/cpu] x86/cpu: Get rid of the " tip-bot2 for Thomas Gleixner
2025-03-04 10:26   ` tip-bot2 for Thomas Gleixner
2025-03-04  8:51 ` [PATCH v1 09/40] x86/cpu: Remove unused TLB strings Ahmed S. Darwish
2025-03-04  9:37   ` [tip: x86/cpu] " tip-bot2 for Thomas Gleixner
2025-03-04 10:26   ` tip-bot2 for Thomas Gleixner
2025-03-04  8:51 ` [PATCH v1 10/40] x86/cpu: Remove leaf 0x2 parsing loop and add helpers Ahmed S. Darwish
2025-03-04  9:26   ` Ingo Molnar
2025-03-05 16:01     ` Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 11/40] x86/cacheinfo: Remove the P4 trace leftovers for real Ahmed S. Darwish
2025-03-04  9:47   ` [tip: x86/cpu] " tip-bot2 for Thomas Gleixner
2025-03-04 10:26   ` tip-bot2 for Thomas Gleixner
2025-03-04  8:51 ` [PATCH v1 12/40] x86/cacheinfo: Remove unnecessary headers and reorder the rest Ahmed S. Darwish
2025-03-04  9:47   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26   ` tip-bot2 for Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 13/40] x86/cacheinfo: Use cpuid leaf 0x2 parsing helpers Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 14/40] x86/cacheinfo: Refactor leaf 0x2 cache descriptor lookup Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 15/40] x86/cacheinfo: Properly name amd_cpuid4()'s first parameter Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 16/40] x86/cacheinfo: Use proper name for cacheinfo instances Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 17/40] x86/cacheinfo: Constify _cpuid4_info_regs instances Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 18/40] x86/cacheinfo: Align ci_info_init() assignment expressions Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 19/40] x86/cacheinfo: Standardize _cpuid4_info_regs instance naming Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 20/40] x86: treewide: Introduce x86_vendor_amd_or_hygon() Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 21/40] x86/cacheinfo: Consolidate AMD/Hygon leaf 0x8000001d calls Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 22/40] x86/cacheinfo: Separate amd_northbridge from _cpuid4_info_regs Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 23/40] x86/cacheinfo: Move AMD cache_disable_0/1 handling to separate file Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 24/40] x86/cacheinfo: Use sysfs_emit() for sysfs attributes show() Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 25/40] x86/cacheinfo: Separate Intel and AMD leaf 0x4 code paths Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 26/40] x86/cacheinfo: Rename _cpuid4_info_regs to _cpuid4_info Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 27/40] x86/cacheinfo: Clarify type markers for leaf 0x2 cache descriptors Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 28/40] x86/cacheinfo: Use enums for cache descriptor types Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 29/40] x86/cpu: Use enums for TLB " Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 30/40] sizes.h: Cover all possible x86 cpu cache sizes Ahmed S. Darwish
2025-03-04  9:35   ` Ingo Molnar
2025-03-05 16:18     ` Ahmed S. Darwish
2025-03-04  9:47   ` [tip: x86/cpu] <linux/sizes.h>: Cover all possible x86 CPU " tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26   ` tip-bot2 for Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 31/40] x86/cpu: Consolidate CPUID leaf 0x2 tables Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 32/40] x86/cacheinfo: Use consolidated leaf 0x2 descriptor table Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 33/40] x86/cpu: " Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 34/40] x86/cacheinfo: Separate leaf 0x2 handling and post-processing logic Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 35/40] x86/cacheinfo: Separate intel leaf 0x4 handling Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 36/40] x86/cacheinfo: Extract out cache level topology ID calculation Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 37/40] x86/cacheinfo: Extract out cache self-snoop checks Ahmed S. Darwish
2025-03-04 10:38   ` Andrew Cooper
2025-03-05 18:40     ` Ahmed S. Darwish
2025-03-05 18:42       ` Andrew Cooper
2025-03-05 18:58         ` Ahmed S. Darwish
2025-03-05 19:01           ` Andrew Cooper
2025-03-04  8:51 ` [PATCH v1 38/40] x86/cacheinfo: Relocate leaf 0x4 cache_type mapping Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 39/40] x86/cacheinfo: Introduce amd_hygon_cpu_has_l3_cache() Ahmed S. Darwish
2025-03-04  8:51 ` [PATCH v1 40/40] x86/cacheinfo: Apply maintainer-tip coding style fixes Ahmed S. Darwish
2025-03-04  9:19 ` [PATCH v1 00/40] x86: Leaf 0x2 and leaf 0x4 refactorings Ingo Molnar
2025-03-04  9:38   ` Ingo Molnar
2025-03-05 17:36     ` Ahmed S. Darwish
2025-03-04  9:33 ` Ingo Molnar
2025-03-05 16:38   ` Ahmed S. Darwish

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20250304085152.51092-4-darwi@linutronix.de \
    --to=darwi@linutronix.de \
    --cc=andrew.cooper3@citrix.com \
    --cc=bp@alien8.de \
    --cc=dave.hansen@linux.intel.com \
    --cc=hpa@zytor.com \
    --cc=john.ogness@linutronix.de \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mingo@redhat.com \
    --cc=tglx@linutronix.de \
    --cc=x86-cpuid@lists.linux.dev \
    --cc=x86@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®