From: "Ahmed S. Darwish" <darwi@linutronix.de>
To: Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
John Ogness <john.ogness@linutronix.de>,
"H. Peter Anvin" <hpa@zytor.com>,
Andrew Cooper <andrew.cooper3@citrix.com>,
x86@kernel.org, x86-cpuid@lists.linux.dev,
LKML <linux-kernel@vger.kernel.org>,
"Ahmed S. Darwish" <darwi@linutronix.de>
Subject: [PATCH v1 06/40] x86/cpu: Use max() for leaf 0x2 TLB descriptors parsing
Date: Tue, 4 Mar 2025 09:51:17 +0100 [thread overview]
Message-ID: <20250304085152.51092-7-darwi@linutronix.de> (raw)
In-Reply-To: <20250304085152.51092-1-darwi@linutronix.de>
The conditional statement "if (x < y) { x = y; }" appears 22 times at
the Intel leaf 0x2 descriptors parsing logic.
Replace each of such instances with a max() expression.
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
arch/x86/kernel/cpu/intel.c | 76 ++++++++++++++-----------------------
1 file changed, 28 insertions(+), 48 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 72f519534e2b..e972c72e2b5d 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -3,6 +3,7 @@
#include <linux/bitops.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/minmax.h>
#include <linux/smp.h>
#include <linux/string.h>
@@ -699,7 +700,9 @@ static const struct _tlb_table intel_tlb_table[] = {
static void intel_tlb_lookup(const unsigned char desc)
{
+ unsigned int entries;
unsigned char k;
+
if (desc == 0)
return;
@@ -711,81 +714,58 @@ static void intel_tlb_lookup(const unsigned char desc)
if (intel_tlb_table[k].tlb_type == 0)
return;
+ entries = intel_tlb_table[k].entries;
switch (intel_tlb_table[k].tlb_type) {
case STLB_4K:
- if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
- if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
+ tlb_lli_4k[ENTRIES] = max(tlb_lli_4k[ENTRIES], entries);
+ tlb_lld_4k[ENTRIES] = max(tlb_lld_4k[ENTRIES], entries);
break;
case STLB_4K_2M:
- if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
- if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
- if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
- if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
- if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
- if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
+ tlb_lli_4k[ENTRIES] = max(tlb_lli_4k[ENTRIES], entries);
+ tlb_lld_4k[ENTRIES] = max(tlb_lld_4k[ENTRIES], entries);
+ tlb_lli_2m[ENTRIES] = max(tlb_lli_2m[ENTRIES], entries);
+ tlb_lld_2m[ENTRIES] = max(tlb_lld_2m[ENTRIES], entries);
+ tlb_lli_4m[ENTRIES] = max(tlb_lli_4m[ENTRIES], entries);
+ tlb_lld_4m[ENTRIES] = max(tlb_lld_4m[ENTRIES], entries);
break;
case TLB_INST_ALL:
- if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
- if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
- if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
+ tlb_lli_4k[ENTRIES] = max(tlb_lli_4k[ENTRIES], entries);
+ tlb_lli_2m[ENTRIES] = max(tlb_lli_2m[ENTRIES], entries);
+ tlb_lli_4m[ENTRIES] = max(tlb_lli_4m[ENTRIES], entries);
break;
case TLB_INST_4K:
- if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
+ tlb_lli_4k[ENTRIES] = max(tlb_lli_4k[ENTRIES], entries);
break;
case TLB_INST_4M:
- if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
+ tlb_lli_4m[ENTRIES] = max(tlb_lli_4m[ENTRIES], entries);
break;
case TLB_INST_2M_4M:
- if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
- if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
+ tlb_lli_2m[ENTRIES] = max(tlb_lli_2m[ENTRIES], entries);
+ tlb_lli_4m[ENTRIES] = max(tlb_lli_4m[ENTRIES], entries);
break;
case TLB_DATA_4K:
case TLB_DATA0_4K:
- if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
+ tlb_lld_4k[ENTRIES] = max(tlb_lld_4k[ENTRIES], entries);
break;
case TLB_DATA_4M:
case TLB_DATA0_4M:
- if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
+ tlb_lld_4m[ENTRIES] = max(tlb_lld_4m[ENTRIES], entries);
break;
case TLB_DATA_2M_4M:
case TLB_DATA0_2M_4M:
- if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
- if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
+ tlb_lld_2m[ENTRIES] = max(tlb_lld_2m[ENTRIES], entries);
+ tlb_lld_4m[ENTRIES] = max(tlb_lld_4m[ENTRIES], entries);
break;
case TLB_DATA_4K_4M:
- if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
- if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
+ tlb_lld_4k[ENTRIES] = max(tlb_lld_4k[ENTRIES], entries);
+ tlb_lld_4m[ENTRIES] = max(tlb_lld_4m[ENTRIES], entries);
break;
case TLB_DATA_1G_2M_4M:
- if (tlb_lld_2m[ENTRIES] < TLB_0x63_2M_4M_ENTRIES)
- tlb_lld_2m[ENTRIES] = TLB_0x63_2M_4M_ENTRIES;
- if (tlb_lld_4m[ENTRIES] < TLB_0x63_2M_4M_ENTRIES)
- tlb_lld_4m[ENTRIES] = TLB_0x63_2M_4M_ENTRIES;
+ tlb_lld_2m[ENTRIES] = max(tlb_lld_2m[ENTRIES], TLB_0x63_2M_4M_ENTRIES);
+ tlb_lld_4m[ENTRIES] = max(tlb_lld_4m[ENTRIES], TLB_0x63_2M_4M_ENTRIES);
fallthrough;
case TLB_DATA_1G:
- if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
- tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
+ tlb_lld_1g[ENTRIES] = max(tlb_lld_1g[ENTRIES], entries);
break;
}
}
--
2.48.1
next prev parent reply other threads:[~2025-03-04 8:52 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-04 8:51 [PATCH v1 00/40] x86: Leaf 0x2 and leaf 0x4 refactorings Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 01/40] x86/cacheinfo: Validate cpuid leaf 0x2 EDX output Ahmed S. Darwish
2025-03-04 9:37 ` [tip: x86/urgent] x86/cacheinfo: Validate CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 02/40] x86/cpu: Validate cpuid " Ahmed S. Darwish
2025-03-04 9:37 ` [tip: x86/urgent] x86/cpu: Validate CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 03/40] x86/cpu: Properly parse leaf 0x2 TLB descriptor 0x63 Ahmed S. Darwish
2025-03-04 9:37 ` [tip: x86/urgent] x86/cpu: Properly parse CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 04/40] x86/cpuid: Include linux/build_bug.h Ahmed S. Darwish
2025-03-04 9:37 ` [tip: x86/cpu] x86/cpuid: Include <linux/build_bug.h> in <asm/cpuid.h> tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26 ` tip-bot2 for Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 05/40] x86/cpu: Remove unnecessary headers and reorder the rest Ahmed S. Darwish
2025-03-04 9:14 ` Ingo Molnar
2025-03-04 9:28 ` Ahmed S. Darwish
2025-03-04 9:37 ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26 ` tip-bot2 for Ahmed S. Darwish
2025-03-04 8:51 ` Ahmed S. Darwish [this message]
2025-03-04 9:37 ` [tip: x86/cpu] x86/cpu: Use max() for CPUID leaf 0x2 TLB descriptors parsing tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26 ` tip-bot2 for Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 07/40] x86/cpu: Simplify TLB entry count storage Ahmed S. Darwish
2025-03-04 9:37 ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26 ` tip-bot2 for Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 08/40] x86/cpu: Get rid of smp_store_cpu_info() indirection Ahmed S. Darwish
2025-03-04 9:37 ` [tip: x86/cpu] x86/cpu: Get rid of the " tip-bot2 for Thomas Gleixner
2025-03-04 10:26 ` tip-bot2 for Thomas Gleixner
2025-03-04 8:51 ` [PATCH v1 09/40] x86/cpu: Remove unused TLB strings Ahmed S. Darwish
2025-03-04 9:37 ` [tip: x86/cpu] " tip-bot2 for Thomas Gleixner
2025-03-04 10:26 ` tip-bot2 for Thomas Gleixner
2025-03-04 8:51 ` [PATCH v1 10/40] x86/cpu: Remove leaf 0x2 parsing loop and add helpers Ahmed S. Darwish
2025-03-04 9:26 ` Ingo Molnar
2025-03-05 16:01 ` Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 11/40] x86/cacheinfo: Remove the P4 trace leftovers for real Ahmed S. Darwish
2025-03-04 9:47 ` [tip: x86/cpu] " tip-bot2 for Thomas Gleixner
2025-03-04 10:26 ` tip-bot2 for Thomas Gleixner
2025-03-04 8:51 ` [PATCH v1 12/40] x86/cacheinfo: Remove unnecessary headers and reorder the rest Ahmed S. Darwish
2025-03-04 9:47 ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26 ` tip-bot2 for Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 13/40] x86/cacheinfo: Use cpuid leaf 0x2 parsing helpers Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 14/40] x86/cacheinfo: Refactor leaf 0x2 cache descriptor lookup Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 15/40] x86/cacheinfo: Properly name amd_cpuid4()'s first parameter Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 16/40] x86/cacheinfo: Use proper name for cacheinfo instances Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 17/40] x86/cacheinfo: Constify _cpuid4_info_regs instances Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 18/40] x86/cacheinfo: Align ci_info_init() assignment expressions Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 19/40] x86/cacheinfo: Standardize _cpuid4_info_regs instance naming Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 20/40] x86: treewide: Introduce x86_vendor_amd_or_hygon() Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 21/40] x86/cacheinfo: Consolidate AMD/Hygon leaf 0x8000001d calls Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 22/40] x86/cacheinfo: Separate amd_northbridge from _cpuid4_info_regs Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 23/40] x86/cacheinfo: Move AMD cache_disable_0/1 handling to separate file Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 24/40] x86/cacheinfo: Use sysfs_emit() for sysfs attributes show() Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 25/40] x86/cacheinfo: Separate Intel and AMD leaf 0x4 code paths Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 26/40] x86/cacheinfo: Rename _cpuid4_info_regs to _cpuid4_info Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 27/40] x86/cacheinfo: Clarify type markers for leaf 0x2 cache descriptors Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 28/40] x86/cacheinfo: Use enums for cache descriptor types Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 29/40] x86/cpu: Use enums for TLB " Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 30/40] sizes.h: Cover all possible x86 cpu cache sizes Ahmed S. Darwish
2025-03-04 9:35 ` Ingo Molnar
2025-03-05 16:18 ` Ahmed S. Darwish
2025-03-04 9:47 ` [tip: x86/cpu] <linux/sizes.h>: Cover all possible x86 CPU " tip-bot2 for Ahmed S. Darwish
2025-03-04 10:26 ` tip-bot2 for Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 31/40] x86/cpu: Consolidate CPUID leaf 0x2 tables Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 32/40] x86/cacheinfo: Use consolidated leaf 0x2 descriptor table Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 33/40] x86/cpu: " Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 34/40] x86/cacheinfo: Separate leaf 0x2 handling and post-processing logic Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 35/40] x86/cacheinfo: Separate intel leaf 0x4 handling Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 36/40] x86/cacheinfo: Extract out cache level topology ID calculation Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 37/40] x86/cacheinfo: Extract out cache self-snoop checks Ahmed S. Darwish
2025-03-04 10:38 ` Andrew Cooper
2025-03-05 18:40 ` Ahmed S. Darwish
2025-03-05 18:42 ` Andrew Cooper
2025-03-05 18:58 ` Ahmed S. Darwish
2025-03-05 19:01 ` Andrew Cooper
2025-03-04 8:51 ` [PATCH v1 38/40] x86/cacheinfo: Relocate leaf 0x4 cache_type mapping Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 39/40] x86/cacheinfo: Introduce amd_hygon_cpu_has_l3_cache() Ahmed S. Darwish
2025-03-04 8:51 ` [PATCH v1 40/40] x86/cacheinfo: Apply maintainer-tip coding style fixes Ahmed S. Darwish
2025-03-04 9:19 ` [PATCH v1 00/40] x86: Leaf 0x2 and leaf 0x4 refactorings Ingo Molnar
2025-03-04 9:38 ` Ingo Molnar
2025-03-05 17:36 ` Ahmed S. Darwish
2025-03-04 9:33 ` Ingo Molnar
2025-03-05 16:38 ` Ahmed S. Darwish
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