* [PATCH v7 1/6] arm64: dts: qcom: x1e80100: Add CAMCC block definition
2025-04-17 11:27 [PATCH v7 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
@ 2025-04-17 11:27 ` Bryan O'Donoghue
2025-04-17 11:27 ` [PATCH v7 2/6] arm64: dts: qcom: x1e80100: Add CCI definitions Bryan O'Donoghue
` (5 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Bryan O'Donoghue @ 2025-04-17 11:27 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Robert Foss, Todor Tomov,
Mauro Carvalho Chehab, Konrad Dybcio
Cc: Krzysztof Kozlowski, linux-arm-msm, linux-clk, devicetree,
linux-kernel, linux-media, Bryan O'Donoghue,
Vladimir Zapolskiy, Konrad Dybcio
Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration
of previous CAMCC blocks with the exception of having two required
power-domains not just one.
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 46b79fce92c90d969e3de48bc88e27915d1592bb..17e044dbb3b6de278d446eaf448561333e407843 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
+#include <dt-bindings/clock/qcom,x1e80100-camcc.h>
#include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
#include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
@@ -5116,6 +5117,22 @@ usb_1_ss1_dwc3_ss: endpoint {
};
};
+ camcc: clock-controller@ade0000 {
+ compatible = "qcom,x1e80100-camcc";
+ reg = <0x0 0x0ade0000 0x0 0x20000>;
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
mdss: display-subsystem@ae00000 {
compatible = "qcom,x1e80100-mdss";
reg = <0 0x0ae00000 0 0x1000>;
--
2.49.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v7 2/6] arm64: dts: qcom: x1e80100: Add CCI definitions
2025-04-17 11:27 [PATCH v7 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
2025-04-17 11:27 ` [PATCH v7 1/6] arm64: dts: qcom: x1e80100: Add CAMCC block definition Bryan O'Donoghue
@ 2025-04-17 11:27 ` Bryan O'Donoghue
2025-04-17 11:27 ` [PATCH v7 3/6] arm64: dts: qcom: x1e80100: Add CAMSS block definition Bryan O'Donoghue
` (4 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Bryan O'Donoghue @ 2025-04-17 11:27 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Robert Foss, Todor Tomov,
Mauro Carvalho Chehab, Konrad Dybcio
Cc: Krzysztof Kozlowski, linux-arm-msm, linux-clk, devicetree,
linux-kernel, linux-media, Bryan O'Donoghue, Konrad Dybcio,
Vladimir Zapolskiy
Add in two CCI busses.
One bus has two CCI bus master pinouts:
cci_i2c_sda0 = gpio101
cci_i2c_scl0 = gpio102
cci_i2c_sda1 = gpio103
cci_i2c_scl1 = gpio104
The second bus has two CCI bus master pinouts:
cci_i2c_sda2 = gpio105
cci_i2c_scl2 = gpio106
aon_cci_i2c_sda3 = gpio235
aon_cci_i2c_scl3 = gpio236
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 150 +++++++++++++++++++++++++++++++++
1 file changed, 150 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 17e044dbb3b6de278d446eaf448561333e407843..3ef3ebde4b2476c1da1fe11383718fba5ff87f85 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5117,6 +5117,84 @@ usb_1_ss1_dwc3_ss: endpoint {
};
};
+ cci0: cci@ac15000 {
+ compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0ac15000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cci";
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ pinctrl-0 = <&cci0_default>;
+ pinctrl-1 = <&cci0_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac16000 {
+ compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0ac16000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cci";
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ pinctrl-0 = <&cci1_default>;
+ pinctrl-1 = <&cci1_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
camcc: clock-controller@ade0000 {
compatible = "qcom,x1e80100-camcc";
reg = <0x0 0x0ade0000 0x0 0x20000>;
@@ -5741,6 +5819,78 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 239>;
wakeup-parent = <&pdc>;
+ cci0_default: cci0-default-state {
+ cci0_i2c0_default: cci0-i2c0-default-pins {
+ /* cci_i2c_sda0, cci_i2c_scl0 */
+ pins = "gpio101", "gpio102";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci0_i2c1_default: cci0-i2c1-default-pins {
+ /* cci_i2c_sda1, cci_i2c_scl1 */
+ pins = "gpio103", "gpio104";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci0_sleep: cci0-sleep-state {
+ cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
+ /* cci_i2c_sda0, cci_i2c_scl0 */
+ pins = "gpio101", "gpio102";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
+ /* cci_i2c_sda1, cci_i2c_scl1 */
+ pins = "gpio103", "gpio104";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_default: cci1-default-state {
+ cci1_i2c0_default: cci1-i2c0-default-pins {
+ /* cci_i2c_sda2, cci_i2c_scl2 */
+ pins = "gpio105","gpio106";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci1_i2c1_default: cci1-i2c1-default-pins {
+ /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */
+ pins = "gpio235","gpio236";
+ function = "aon_cci";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci1_sleep: cci1-sleep-state {
+ cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
+ /* cci_i2c_sda2, cci_i2c_scl2 */
+ pins = "gpio105","gpio106";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
+ /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */
+ pins = "gpio235","gpio236";
+ function = "aon_cci";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
qup_i2c0_data_clk: qup-i2c0-data-clk-state {
/* SDA, SCL */
pins = "gpio0", "gpio1";
--
2.49.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v7 3/6] arm64: dts: qcom: x1e80100: Add CAMSS block definition
2025-04-17 11:27 [PATCH v7 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
2025-04-17 11:27 ` [PATCH v7 1/6] arm64: dts: qcom: x1e80100: Add CAMCC block definition Bryan O'Donoghue
2025-04-17 11:27 ` [PATCH v7 2/6] arm64: dts: qcom: x1e80100: Add CCI definitions Bryan O'Donoghue
@ 2025-04-17 11:27 ` Bryan O'Donoghue
2025-04-17 11:27 ` [PATCH v7 4/6] arm64: dts: qcom: x1e80100-crd: Define RGB camera clock and reset pinout Bryan O'Donoghue
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Bryan O'Donoghue @ 2025-04-17 11:27 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Robert Foss, Todor Tomov,
Mauro Carvalho Chehab, Konrad Dybcio
Cc: Krzysztof Kozlowski, linux-arm-msm, linux-clk, devicetree,
linux-kernel, linux-media, Bryan O'Donoghue, Konrad Dybcio,
Vladimir Zapolskiy
Add dtsi to describe the xe180100 CAMSS block
4 x CSIPHY
2 x CSID
2 x CSID Lite
2 x IFE
2 x IFE Lite
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 185 +++++++++++++++++++++++++++++++++
1 file changed, 185 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 3ef3ebde4b2476c1da1fe11383718fba5ff87f85..01a33005969d7df132b1aca26cb0884828c3c8ea 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5195,6 +5195,191 @@ cci1_i2c1: i2c-bus@1 {
};
};
+ camss: isp@acb6000 {
+ compatible = "qcom,x1e80100-camss";
+
+ reg = <0x0 0x0acb7000 0x0 0x2000>,
+ <0x0 0x0acb9000 0x0 0x2000>,
+ <0x0 0x0acbb000 0x0 0x2000>,
+ <0x0 0x0acc6000 0x0 0x1000>,
+ <0x0 0x0acca000 0x0 0x1000>,
+ <0x0 0x0acb6000 0x0 0x1000>,
+ <0x0 0x0ace4000 0x0 0x2000>,
+ <0x0 0x0ace6000 0x0 0x2000>,
+ <0x0 0x0ace8000 0x0 0x2000>,
+ <0x0 0x0acec000 0x0 0x2000>,
+ <0x0 0x0acf6000 0x0 0x1000>,
+ <0x0 0x0acf7000 0x0 0x1000>,
+ <0x0 0x0acf8000 0x0 0x1000>,
+ <0x0 0x0ac62000 0x0 0x4000>,
+ <0x0 0x0ac71000 0x0 0x4000>,
+ <0x0 0x0acc7000 0x0 0x2000>,
+ <0x0 0x0accb000 0x0 0x2000>;
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csid_wrapper",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy4",
+ "csitpg0",
+ "csitpg1",
+ "csitpg2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
+ <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+ clock-names = "camnoc_nrt_axi",
+ "camnoc_rt_axi",
+ "core_ahb",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe_lite",
+ "cphy_rx_clk_src",
+ "csid",
+ "csid_csiphy_rx",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy4",
+ "vfe0",
+ "vfe1",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc",
+ "sf_mnoc",
+ "sf_icp_mnoc";
+
+ iommus = <&apps_smmu 0x800 0x60>,
+ <&apps_smmu 0x860 0x60>,
+ <&apps_smmu 0x1800 0x60>,
+ <&apps_smmu 0x1860 0x60>,
+ <&apps_smmu 0x18e0 0x00>,
+ <&apps_smmu 0x1900 0x00>,
+ <&apps_smmu 0x1980 0x20>,
+ <&apps_smmu 0x19a0 0x20>;
+
+ power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+ <&camcc CAM_CC_IFE_1_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "top";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
camcc: clock-controller@ade0000 {
compatible = "qcom,x1e80100-camcc";
reg = <0x0 0x0ade0000 0x0 0x20000>;
--
2.49.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v7 4/6] arm64: dts: qcom: x1e80100-crd: Define RGB camera clock and reset pinout
2025-04-17 11:27 [PATCH v7 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
` (2 preceding siblings ...)
2025-04-17 11:27 ` [PATCH v7 3/6] arm64: dts: qcom: x1e80100: Add CAMSS block definition Bryan O'Donoghue
@ 2025-04-17 11:27 ` Bryan O'Donoghue
2025-04-17 11:27 ` [PATCH v7 5/6] arm64: dts: qcom: x1e80100-crd: Add pm8010 CRD pmic,id=m regulators Bryan O'Donoghue
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Bryan O'Donoghue @ 2025-04-17 11:27 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Robert Foss, Todor Tomov,
Mauro Carvalho Chehab, Konrad Dybcio
Cc: Krzysztof Kozlowski, linux-arm-msm, linux-clk, devicetree,
linux-kernel, linux-media, Bryan O'Donoghue
The RGB camera sensor uses MCLK3/gpio100 as clock with CAM_RESET_N/gpio237
as reset.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/x1-crd.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
index f73f053a46a08d875acdeeef9ac195a9b857ae3f..e2f6e342db7e2f7cfbda17cbe28199546de5449d 100644
--- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
@@ -1460,6 +1460,22 @@ &tlmm {
<44 4>, /* SPI (TPM) */
<238 1>; /* UFS Reset */
+ cam_rgb_default: cam-rgb-default-state {
+ mclk-pins {
+ pins = "gpio100";
+ function = "cam_aon";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ reset-n-pins {
+ pins = "gpio237";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
edp_reg_en: edp-reg-en-state {
pins = "gpio70";
function = "gpio";
--
2.49.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v7 5/6] arm64: dts: qcom: x1e80100-crd: Add pm8010 CRD pmic,id=m regulators
2025-04-17 11:27 [PATCH v7 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
` (3 preceding siblings ...)
2025-04-17 11:27 ` [PATCH v7 4/6] arm64: dts: qcom: x1e80100-crd: Define RGB camera clock and reset pinout Bryan O'Donoghue
@ 2025-04-17 11:27 ` Bryan O'Donoghue
2025-04-25 20:59 ` Konrad Dybcio
2025-04-17 11:27 ` [PATCH v7 6/6] arm64: dts: qcom: x1e80100-crd: Define RGB sensor for cci1_i2c1 Bryan O'Donoghue
2025-04-17 13:51 ` [PATCH v7 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Rob Herring (Arm)
6 siblings, 1 reply; 11+ messages in thread
From: Bryan O'Donoghue @ 2025-04-17 11:27 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Robert Foss, Todor Tomov,
Mauro Carvalho Chehab, Konrad Dybcio
Cc: Krzysztof Kozlowski, linux-arm-msm, linux-clk, devicetree,
linux-kernel, linux-media, Bryan O'Donoghue
Add pmic,id = m rpmh to regulator definitions. This regulator set provides
vreg_l3m_1p8 the regulator for the ov08x40 RGB sensor on the CRD.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/x1-crd.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
index e2f6e342db7e2f7cfbda17cbe28199546de5449d..74bf2f48d93522d3f5b7ca990c06519ca664d905 100644
--- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
@@ -858,6 +858,36 @@ vreg_l3j_0p8: ldo3 {
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
+
+ regulators-8 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "m";
+
+ vdd-l1-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-l4-supply = <&vreg_s4c_1p8>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ vreg_l3m_1p8: ldo3 {
+ regulator-name = "vreg_l3m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1808000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vrer_l4m_1p8: ldo4 {
+ regulator-name = "vrer_l4m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1808000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p9: ldo7 {
+ regulator-name = "vreg_l7m_2p9";
+ regulator-min-microvolt = <2912000>;
+ regulator-max-microvolt = <2912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
};
&gpu {
--
2.49.0
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v7 5/6] arm64: dts: qcom: x1e80100-crd: Add pm8010 CRD pmic,id=m regulators
2025-04-17 11:27 ` [PATCH v7 5/6] arm64: dts: qcom: x1e80100-crd: Add pm8010 CRD pmic,id=m regulators Bryan O'Donoghue
@ 2025-04-25 20:59 ` Konrad Dybcio
0 siblings, 0 replies; 11+ messages in thread
From: Konrad Dybcio @ 2025-04-25 20:59 UTC (permalink / raw)
To: Bryan O'Donoghue, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Robert Foss, Todor Tomov, Mauro Carvalho Chehab, Konrad Dybcio
Cc: Krzysztof Kozlowski, linux-arm-msm, linux-clk, devicetree,
linux-kernel, linux-media
On 4/17/25 1:27 PM, Bryan O'Donoghue wrote:
> Add pmic,id = m rpmh to regulator definitions. This regulator set provides
> vreg_l3m_1p8 the regulator for the ov08x40 RGB sensor on the CRD.
>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/x1-crd.dtsi | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
> index e2f6e342db7e2f7cfbda17cbe28199546de5449d..74bf2f48d93522d3f5b7ca990c06519ca664d905 100644
> --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
> @@ -858,6 +858,36 @@ vreg_l3j_0p8: ldo3 {
> regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> };
> };
> +
> + regulators-8 {
> + compatible = "qcom,pm8010-rpmh-regulators";
> + qcom,pmic-id = "m";
> +
> + vdd-l1-l2-supply = <&vreg_s5j_1p2>;
> + vdd-l3-l4-supply = <&vreg_s4c_1p8>;
> + vdd-l7-supply = <&vreg_bob1>;
> +
> + vreg_l3m_1p8: ldo3 {
> + regulator-name = "vreg_l3m_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1808000>;
Is this and below +8000mV a fluke?
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vrer_l4m_1p8: ldo4 {
> + regulator-name = "vrer_l4m_1p8";
typo: vrer-vreg
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1808000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> + };
> +
> + vreg_l7m_2p9: ldo7 {
> + regulator-name = "vreg_l7m_2p9";
> + regulator-min-microvolt = <2912000>;
> + regulator-max-microvolt = <2912000>;
PM8010 coupled with SM8450 has:
regulator-min-microvolt = <2912000>;
regulator-max-microvolt = <3304000>;
although the x1e crd schem calls this pin ...2p9 (though the names are
doubtful at times too) - please check if the consumer is happy with 2.9v
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v7 6/6] arm64: dts: qcom: x1e80100-crd: Define RGB sensor for cci1_i2c1
2025-04-17 11:27 [PATCH v7 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
` (4 preceding siblings ...)
2025-04-17 11:27 ` [PATCH v7 5/6] arm64: dts: qcom: x1e80100-crd: Add pm8010 CRD pmic,id=m regulators Bryan O'Donoghue
@ 2025-04-17 11:27 ` Bryan O'Donoghue
2025-04-25 21:01 ` Konrad Dybcio
2025-04-17 13:51 ` [PATCH v7 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Rob Herring (Arm)
6 siblings, 1 reply; 11+ messages in thread
From: Bryan O'Donoghue @ 2025-04-17 11:27 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Robert Foss, Todor Tomov,
Mauro Carvalho Chehab, Konrad Dybcio
Cc: Krzysztof Kozlowski, linux-arm-msm, linux-clk, devicetree,
linux-kernel, linux-media, Bryan O'Donoghue
Define ov08x40 on cci1_i2c1. The RGB sensor appears on the AON CCI pins
connected to CSIPHY4 in four lane mode.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/x1-crd.dtsi | 60 ++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
index 74bf2f48d93522d3f5b7ca990c06519ca664d905..048e49aa805c7239e1a22b59bd784683d1d0da08 100644
--- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
@@ -894,6 +894,66 @@ &gpu {
status = "okay";
};
+&camcc {
+ status = "okay";
+};
+
+&camss {
+ vdd-csiphy-0p8-supply = <&vreg_l2c_0p8>;
+ vdd-csiphy-1p2-supply = <&vreg_l1c_1p2>;
+
+ status = "okay";
+
+ ports {
+ /*
+ * port0 => csiphy0
+ * port1 => csiphy1
+ * port2 => csiphy2
+ * port3 => csiphy4
+ */
+ port@3 {
+ csiphy4_ep: endpoint@4 {
+ reg = <4>;
+ clock-lanes = <7>;
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&ov08x40_ep>;
+ };
+ };
+ };
+};
+
+&cci1 {
+ status = "okay";
+};
+
+&cci1_i2c1 {
+ camera@36 {
+ compatible = "ovti,ov08x40";
+ reg = <0x36>;
+
+ reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cam_rgb_default>;
+
+ clocks = <&camcc CAM_CC_MCLK4_CLK>;
+ assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ orientation = <0>; /* front facing */
+
+ avdd-supply = <&vreg_l7b_2p8>;
+ dovdd-supply = <&vreg_l3m_1p8>;
+
+ port {
+ ov08x40_ep: endpoint {
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <400000000>;
+ remote-endpoint = <&csiphy4_ep>;
+ };
+ };
+ };
+};
+
&i2c0 {
clock-frequency = <400000>;
--
2.49.0
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v7 6/6] arm64: dts: qcom: x1e80100-crd: Define RGB sensor for cci1_i2c1
2025-04-17 11:27 ` [PATCH v7 6/6] arm64: dts: qcom: x1e80100-crd: Define RGB sensor for cci1_i2c1 Bryan O'Donoghue
@ 2025-04-25 21:01 ` Konrad Dybcio
2025-04-25 21:06 ` Bryan O'Donoghue
0 siblings, 1 reply; 11+ messages in thread
From: Konrad Dybcio @ 2025-04-25 21:01 UTC (permalink / raw)
To: Bryan O'Donoghue, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Robert Foss, Todor Tomov, Mauro Carvalho Chehab, Konrad Dybcio
Cc: Krzysztof Kozlowski, linux-arm-msm, linux-clk, devicetree,
linux-kernel, linux-media
On 4/17/25 1:27 PM, Bryan O'Donoghue wrote:
> Define ov08x40 on cci1_i2c1. The RGB sensor appears on the AON CCI pins
> connected to CSIPHY4 in four lane mode.
>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/x1-crd.dtsi | 60 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
> index 74bf2f48d93522d3f5b7ca990c06519ca664d905..048e49aa805c7239e1a22b59bd784683d1d0da08 100644
> --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
> @@ -894,6 +894,66 @@ &gpu {
> status = "okay";
> };
>
> +&camcc {
> + status = "okay";
> +};
CAMCC shall be enabled on all boards unconditionally, if only
for unused clock cleanup to always take place peacefully
> +
> +&camss {
> + vdd-csiphy-0p8-supply = <&vreg_l2c_0p8>;
> + vdd-csiphy-1p2-supply = <&vreg_l1c_1p2>;
> +
> + status = "okay";
> +
> + ports {
> + /*
> + * port0 => csiphy0
> + * port1 => csiphy1
> + * port2 => csiphy2
> + * port3 => csiphy4
> + */
That's SoC-specific AFIACU
> + port@3 {
> + csiphy4_ep: endpoint@4 {
> + reg = <4>;
> + clock-lanes = <7>;
> + data-lanes = <0 1 2 3>;
> + remote-endpoint = <&ov08x40_ep>;
> + };
> + };
> + };
> +};
> +
> +&cci1 {
> + status = "okay";
> +};
> +
> +&cci1_i2c1 {
> + camera@36 {
> + compatible = "ovti,ov08x40";
> + reg = <0x36>;
> +
> + reset-gpios = <&tlmm 237 GPIO_ACTIVE_LOW>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&cam_rgb_default>;
property-n
property-names
please
> +
> + clocks = <&camcc CAM_CC_MCLK4_CLK>;
> + assigned-clocks = <&camcc CAM_CC_MCLK4_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + orientation = <0>; /* front facing */
This most definitely needs a dt binding definition instead of a comment
Konrad
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v7 6/6] arm64: dts: qcom: x1e80100-crd: Define RGB sensor for cci1_i2c1
2025-04-25 21:01 ` Konrad Dybcio
@ 2025-04-25 21:06 ` Bryan O'Donoghue
0 siblings, 0 replies; 11+ messages in thread
From: Bryan O'Donoghue @ 2025-04-25 21:06 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Robert Foss,
Todor Tomov, Mauro Carvalho Chehab, Konrad Dybcio
Cc: Krzysztof Kozlowski, linux-arm-msm, linux-clk, devicetree,
linux-kernel, linux-media
On 25/04/2025 22:01, Konrad Dybcio wrote:
>> + orientation = <0>; /* front facing */
> This most definitely needs a dt binding definition instead of a comment
That's standard somewhere.
But now that you mention it, it should be a define not an integer.
---
bod
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v7 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon
2025-04-17 11:27 [PATCH v7 0/6] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
` (5 preceding siblings ...)
2025-04-17 11:27 ` [PATCH v7 6/6] arm64: dts: qcom: x1e80100-crd: Define RGB sensor for cci1_i2c1 Bryan O'Donoghue
@ 2025-04-17 13:51 ` Rob Herring (Arm)
6 siblings, 0 replies; 11+ messages in thread
From: Rob Herring (Arm) @ 2025-04-17 13:51 UTC (permalink / raw)
To: Bryan O'Donoghue
Cc: Michael Turquette, linux-clk, Krzysztof Kozlowski, Konrad Dybcio,
Stephen Boyd, Robert Foss, Krzysztof Kozlowski, linux-arm-msm,
linux-kernel, Bjorn Andersson, devicetree, Todor Tomov,
Vladimir Zapolskiy, Conor Dooley, linux-media, Konrad Dybcio,
Mauro Carvalho Chehab
On Thu, 17 Apr 2025 12:27:01 +0100, Bryan O'Donoghue wrote:
> Changes in v7:
> - camss compat string is in media-comitters for 6.16 so it should
> be possible to merge the core DTSI stuff in this series now.
> - Adds RB as indicated in previous cycle.
> - Changes <0 0xvalue 0 0xvalue> to <0x0 0xvalue 0x0 0xvalue> per
> current comments on linux-arm-msm.
> - Includes CRD dtsi for the ov08x40.
> - Link to v6: https://lore.kernel.org/r/20250314-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v6-0-edcb2cfc3122@linaro.org
> - Link to media-comitters: https://gitlab.freedesktop.org/linux-media/media-committers
>
> Changes in v6:
> - Removes 'A phandle to an OPP node describing' per Krzysztof's comment
> on patch #1
> - Drops Fixes: from patch #1 - Krzysztof
> - The ordering of opp description MXC and MMXC is kept as it matches the
> power-domain ordering - Krzysztof/bod
> - Link to v5: https://lore.kernel.org/r/20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v5-0-846c9a6493a8@linaro.org
>
> v5:
> - Picks up a Fixes: that is a valid precursor for this series - Vlad
> - Applies RB from Vlad
> - Drops "cam" prefix in interconnect names - Krzysztof/Vlad
> - Amends sorting of regs, clocks consistent with recent 8550 - Depeng/Vlad
> - Link to v4: https://lore.kernel.org/r/20250119-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v4-0-c2964504131c@linaro.org
>
> v4:
> - Applies RB from Konrad
> - Adds the second CCI I2C bus to CCI commit log description.
> I previously considered leaving out the always on pins but, decided
> to include them in the end and forgot to align the commit log.
> - Alphabetises the camcc.h included in the dtsi. - Vlad
> - Link to v3: https://lore.kernel.org/r/20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-0-cb66d55d20cc@linaro.org
>
> v3:
> - Fixes ordering of headers in dtsi - Vlad
> - Changes camcc to always on - Vlad
> - Applies RB as indicated - Krzysztof, Konrad
> - Link to v2: https://lore.kernel.org/r/20241227-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v2-0-06fdd5a7d5bb@linaro.org
>
> v2:
>
> I've gone through each comment and implemented each suggestion since IMO
> they were all good/correct comments.
>
> Detail:
>
> - Moves x1e80100 camcc to its own yaml - Krzysztof
> - csid_wrapper comes first because it is the most relevant
> register set - configuring all CSID blocks subordinate to it - bod, Krzysztof
> - Fixes missing commit log - Krz
> - Updates to latest format established @ sc7280 - bod
> - Includes CSID lite which I forgot to add @ v1 - Konrad, bod
> - Replaces static ICC parameters with defines - Konrad
> - Drops newlines between x and x-name - Konrad
> - Drops redundant iommu extents - Konrad
> - Leaves CAMERA_AHB_CLK as-is - Kronrad, Dmitry
> Link: https://lore.kernel.org/r/3f1a960f-062e-4c29-ae7d-126192f35a8b@oss.qualcomm.com
> - Interrupt EDGE_RISING - Vladimir
> - Implements suggested regulator names pending refactor to PHY API - Vladimir
> - Drop slow_ahb_src clock - Vladimir
>
> Link to v1:
> https://lore.kernel.org/r/20241119-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v1-0-54075d75f654@linaro.org
>
> Working tree:
> https://git.codelinaro.org/bryan.odonoghue/kernel/-/tree/arm-laptop/wip/x1e80100-6.13-rc3
>
> v1:
>
> This series adds dt-bindings and dtsi for CAMSS on x1e80100.
>
> The primary difference between x1e80100 and other platforms is a new VFE
> and CSID pair at version 680.
>
> Some minor driver churn will be required to support outside of the new VFE
> and CSID blocks but nothing too major.
>
> The CAMCC in this silicon requires two, not one power-domain requiring
> either this fix I've proposed here or something similar:
>
> https://lore.kernel.org/linux-arm-msm/bad60452-41b3-42fb-acba-5b7226226d2d@linaro.org/T/#t
>
> That doesn't gate adoption of the binding description though.
>
> A working tree in progress can be found here:
> https://git.codelinaro.org/bryan.odonoghue/kernel/-/tree/x1e80100-6.12-rc7+camss?ref_type=heads
>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> Bryan O'Donoghue (6):
> arm64: dts: qcom: x1e80100: Add CAMCC block definition
> arm64: dts: qcom: x1e80100: Add CCI definitions
> arm64: dts: qcom: x1e80100: Add CAMSS block definition
> arm64: dts: qcom: x1e80100-crd: Define RGB camera clock and reset pinout
> arm64: dts: qcom: x1e80100-crd: Add pm8010 CRD pmic,id=m regulators
> arm64: dts: qcom: x1e80100-crd: Define RGB sensor for cci1_i2c1
>
> arch/arm64/boot/dts/qcom/x1-crd.dtsi | 106 ++++++++++
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 352 +++++++++++++++++++++++++++++++++
> 2 files changed, 458 insertions(+)
> ---
> base-commit: 0316f040a04804ff1f45e51ccd42b45552c54a60
> change-id: 20250313-b4-linux-next-25-03-13-dtsi-x1e80100-camss-1506f74bbd3a
>
> Best regards,
> --
> Bryan O'Donoghue <bryan.odonoghue@linaro.org>
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: using specified base-commit 0316f040a04804ff1f45e51ccd42b45552c54a60
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20250417-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-3fd4124cf35a@linaro.org:
arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dtb: /soc@0/isp@acb6000: failed to match any schema with compatible: ['qcom,x1e80100-camss']
arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dtb: /soc@0/isp@acb6000: failed to match any schema with compatible: ['qcom,x1e80100-camss']
arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dtb: /soc@0/isp@acb6000: failed to match any schema with compatible: ['qcom,x1e80100-camss']
arch/arm64/boot/dts/qcom/x1p42100-crd.dtb: /soc@0/isp@acb6000: failed to match any schema with compatible: ['qcom,x1e80100-camss']
arch/arm64/boot/dts/qcom/x1e001de-devkit.dtb: /soc@0/isp@acb6000: failed to match any schema with compatible: ['qcom,x1e80100-camss']
arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dtb: /soc@0/isp@acb6000: failed to match any schema with compatible: ['qcom,x1e80100-camss']
arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: /soc@0/isp@acb6000: failed to match any schema with compatible: ['qcom,x1e80100-camss']
arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtb: /soc@0/isp@acb6000: failed to match any schema with compatible: ['qcom,x1e80100-camss']
arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dtb: /soc@0/isp@acb6000: failed to match any schema with compatible: ['qcom,x1e80100-camss']
arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus15.dtb: /soc@0/isp@acb6000: failed to match any schema with compatible: ['qcom,x1e80100-camss']
arch/arm64/boot/dts/qcom/x1e80100-crd.dtb: /soc@0/isp@acb6000: failed to match any schema with compatible: ['qcom,x1e80100-camss']
arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus13.dtb: /soc@0/isp@acb6000: failed to match any schema with compatible: ['qcom,x1e80100-camss']
^ permalink raw reply [flat|nested] 11+ messages in thread