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* [PATCH] riscv: dts: sophgo: fix DMA data-width configuration for CV18xx
@ 2025-04-28  9:24 Ze Huang
  2025-04-30  6:11 ` Inochi Amaoto
  2025-04-30  6:54 ` Inochi Amaoto
  0 siblings, 2 replies; 4+ messages in thread
From: Ze Huang @ 2025-04-28  9:24 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen Wang,
	Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Alexandre Ghiti
  Cc: devicetree, sophgo, linux-riscv, linux-kernel, Yu Yuan, Ze Huang,
	Ze Huang

The "snps,data-width" property[1] defines the AXI data width of the DMA
controller as:

    width = 8 × (2^n) bits

(0 = 8 bits, 1 = 16 bits, 2 = 32 bits, ..., 6 = 512 bits)
where "n" is the value of "snps,data-width".

For the CV18xx DMA controller, the correct AXI data width is 32 bits,
corresponding to "snps,data-width = 2".

Test results on Milkv Duo S can be found here [2].

Link: https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/dma/snps%2Cdw-axi-dmac.yaml#L74 [1]
Link: https://gist.github.com/Sutter099/4fa99bb2d89e5af975983124704b3861 [2]

Co-developed-by: Yu Yuan <yu.yuan@sjtu.edu.cn>
Signed-off-by: Yu Yuan <yu.yuan@sjtu.edu.cn>
Signed-off-by: Ze Huang <huange@whut.edu.cn>
---
Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
 arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index c18822ec849f353bc296965d2d600a3df314cff6..58cd546392e056a3bbdf9c27a73c050de1060fba 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -341,7 +341,7 @@ dmac: dma-controller@4330000 {
 					   1024 1024 1024 1024>;
 			snps,priority = <0 1 2 3 4 5 6 7>;
 			snps,dma-masters = <2>;
-			snps,data-width = <4>;
+			snps,data-width = <2>;
 			status = "disabled";
 		};
 

---
base-commit: b4432656b36e5cc1d50a1f2dc15357543add530e
change-id: 20250428-duo-dma-config-feb4e5e0546f

Best regards,
-- 
Ze Huang <huangze@whut.edu.cn>


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] riscv: dts: sophgo: fix DMA data-width configuration for CV18xx
  2025-04-28  9:24 [PATCH] riscv: dts: sophgo: fix DMA data-width configuration for CV18xx Ze Huang
@ 2025-04-30  6:11 ` Inochi Amaoto
  2025-04-30  6:54 ` Inochi Amaoto
  1 sibling, 0 replies; 4+ messages in thread
From: Inochi Amaoto @ 2025-04-30  6:11 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen Wang,
	Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
	Ze Huang
  Cc: Inochi Amaoto, devicetree, sophgo, linux-riscv, linux-kernel,
	Yu Yuan, Ze Huang

On Mon, 28 Apr 2025 17:24:36 +0800, Ze Huang wrote:
> The "snps,data-width" property[1] defines the AXI data width of the DMA
> controller as:
> 
>     width = 8 × (2^n) bits
> 
> (0 = 8 bits, 1 = 16 bits, 2 = 32 bits, ..., 6 = 512 bits)
> where "n" is the value of "snps,data-width".
> 
> [...]

Applied to fixes, thanks!

[1/1] riscv: dts: sophgo: fix DMA data-width configuration for CV18xx
      https://github.com/sophgo/linux/commit/32b3f9d3e57bb4bd2204a6a4305b9f899f725859

Thanks,
Inochi


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] riscv: dts: sophgo: fix DMA data-width configuration for CV18xx
  2025-04-28  9:24 [PATCH] riscv: dts: sophgo: fix DMA data-width configuration for CV18xx Ze Huang
  2025-04-30  6:11 ` Inochi Amaoto
@ 2025-04-30  6:54 ` Inochi Amaoto
  2025-05-06 10:17   ` Ze Huang
  1 sibling, 1 reply; 4+ messages in thread
From: Inochi Amaoto @ 2025-04-30  6:54 UTC (permalink / raw)
  To: Ze Huang, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Chen Wang, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
	Albert Ou, Alexandre Ghiti
  Cc: devicetree, sophgo, linux-riscv, linux-kernel, Yu Yuan, Ze Huang

On Mon, Apr 28, 2025 at 05:24:36PM +0800, Ze Huang wrote:
> The "snps,data-width" property[1] defines the AXI data width of the DMA
> controller as:
> 
>     width = 8 × (2^n) bits
> 
> (0 = 8 bits, 1 = 16 bits, 2 = 32 bits, ..., 6 = 512 bits)
> where "n" is the value of "snps,data-width".
> 
> For the CV18xx DMA controller, the correct AXI data width is 32 bits,
> corresponding to "snps,data-width = 2".
> 
> Test results on Milkv Duo S can be found here [2].
> 
> Link: https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/dma/snps%2Cdw-axi-dmac.yaml#L74 [1]
> Link: https://gist.github.com/Sutter099/4fa99bb2d89e5af975983124704b3861 [2]
> 
> Co-developed-by: Yu Yuan <yu.yuan@sjtu.edu.cn>
> Signed-off-by: Yu Yuan <yu.yuan@sjtu.edu.cn>
> Signed-off-by: Ze Huang <huange@whut.edu.cn>
> ---
> Signed-off-by: Ze Huang <huangze@whut.edu.cn>

I think there is a wrong sob here, also, please add a fixes tag if
you fix something. I will take care of this when merging.

Fixes: 514951a81a5e ("riscv: dts: sophgo: cv18xx: add DMA controller")

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] riscv: dts: sophgo: fix DMA data-width configuration for CV18xx
  2025-04-30  6:54 ` Inochi Amaoto
@ 2025-05-06 10:17   ` Ze Huang
  0 siblings, 0 replies; 4+ messages in thread
From: Ze Huang @ 2025-05-06 10:17 UTC (permalink / raw)
  To: Inochi Amaoto, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Chen Wang, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Alexandre Ghiti
  Cc: devicetree, sophgo, linux-riscv, linux-kernel, Yu Yuan, ze huang

On 4/30/25 2:54 PM, Inochi Amaoto wrote:
> On Mon, Apr 28, 2025 at 05:24:36PM +0800, Ze Huang wrote:
>> The "snps,data-width" property[1] defines the AXI data width of the DMA
>> controller as:
>>
>>      width = 8 × (2^n) bits
>>
>> (0 = 8 bits, 1 = 16 bits, 2 = 32 bits, ..., 6 = 512 bits)
>> where "n" is the value of "snps,data-width".
>>
>> For the CV18xx DMA controller, the correct AXI data width is 32 bits,
>> corresponding to "snps,data-width = 2".
>>
>> Test results on Milkv Duo S can be found here [2].
>>
>> Link: https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/dma/snps%2Cdw-axi-dmac.yaml#L74 [1]
>> Link: https://gist.github.com/Sutter099/4fa99bb2d89e5af975983124704b3861 [2]
>>
>> Co-developed-by: Yu Yuan <yu.yuan@sjtu.edu.cn>
>> Signed-off-by: Yu Yuan <yu.yuan@sjtu.edu.cn>

>> Signed-off-by: Ze Huang <huange@whut.edu.cn>

>> ---
>> Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> I think there is a wrong sob here,

Yeah... There's a typo in mail address.

> also, please add a fixes tag if
> you fix something. I will take care of this when merging.
>
> Fixes: 514951a81a5e ("riscv: dts: sophgo: cv18xx: add DMA controller")
>

Thank you for your review and reminder. I will follow that :-)


^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2025-05-06 10:23 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2025-04-28  9:24 [PATCH] riscv: dts: sophgo: fix DMA data-width configuration for CV18xx Ze Huang
2025-04-30  6:11 ` Inochi Amaoto
2025-04-30  6:54 ` Inochi Amaoto
2025-05-06 10:17   ` Ze Huang

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