* [PATCH v3 00/14 RESEND] Add clock support for Exynos8855 SoC [not found] <CGME20261113104829epcas5p13695795bc337b89816b05eec610a0dba@epcas5p1.samsung.com> @ 2026-11-13 11:05 ` Raghav Sharma [not found] ` <CGME20261113104832epcas5p4e1e9a3dedeb0c9c60cb80c23eb5d930d@epcas5p4.samsung.com> ` (13 more replies) 0 siblings, 14 replies; 21+ messages in thread From: Raghav Sharma @ 2026-11-13 11:05 UTC (permalink / raw) To: krzk, s.nawrocki, cw00.choi, peter.griffin, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, raghav.s Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy This patch series adds clock support for below blocks found in Exynos8855 SoC TOP & PERIC PERIS HSI USB There are many other blocks, for which the support will be added in a forthcoming patch series. Signed-off-by: Raghav Sharma <raghav.s@samsung.com> --- Chanegs in v3: - Addressed Sashiko review comments - Collected Reviewed-by tags - In patch#2, added samsung,sysreg property to the binding, somehow this was not cought by dt_binding_check Have kept reviewed-by of Krzysztof on this patch Changes in v2: - Removed name duplicates login, as pointed by Krzysztof Kozlowski -Corrected the sequence of binding, driver and DT entries - Removed <linux/mod_devicetable.h>, as pointed by Uwe - Added all the TOP clocks in single patch - Organised the patches in the order: dt-bindings → clk-driver → dtsi - Added Automatic Clock Gating, as suggested by Peter Griffin -Since we are adding ACG, we need to add SYSREG, hence, added that - Followed the name mangling strategy as mentioned in clk-gs101 Link to v2: https://lore.kernel.org/all/20261009120137.2801911-1-raghav.s@samsung.com/ Link to v1: https://lore.kernel.org/all/20260728121111.2077860-1-raghav.s@samsung.com/ Alim Akhtar (2): dt-bindings: soc: samsung: Exynos8855 SYSREG compatibles clk: samsung: clk-pll: Add support for pll_4313 Raghav Sharma (12): dt-bindings: clock: exynos8855: add top & peric clock definitions dt-bindings: clock: exynos8855: add peris clock definitions dt-bindings: clock: exynos8855: add hsi clock definitions dt-bindings: clock: exynos8855: add usb clock definitions clk: samsung: exynos8855: add block top and peric clock support clk: samsung: exynos8855: add block peris clock support clk: samsung: exynos8855: add block hsi clock support clk: samsung: exynos8855: add block usb clock support arm64: dts: exynos8855: add cmu_top & cmu_peric clock DT nodes arm64: dts: exynos8855: add cmu_peris clock DT nodes arm64: dts: exynos8855: add cmu_hsi clock DT nodes arm64: dts: exynos8855: add cmu_usb clock DT nodes .../clock/samsung,exynos8855-clock.yaml | 196 +++ .../soc/samsung/samsung,exynos-sysreg.yaml | 8 + arch/arm64/boot/dts/exynos/exynos8855.dtsi | 95 ++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos8855.c | 1378 +++++++++++++++++ drivers/clk/samsung/clk-pll.c | 11 +- drivers/clk/samsung/clk-pll.h | 1 + .../dt-bindings/clock/samsung,exynos8855.h | 233 +++ 8 files changed, 1922 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml create mode 100644 drivers/clk/samsung/clk-exynos8855.c create mode 100644 include/dt-bindings/clock/samsung,exynos8855.h base-commit: b810335a0699d1810683796b0e3ffe8827ddfe6c -- 2.34.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <CGME20261113104832epcas5p4e1e9a3dedeb0c9c60cb80c23eb5d930d@epcas5p4.samsung.com>]
* [PATCH v3 01/14 RESEND] dt-bindings: soc: samsung: Exynos8855 SYSREG compatibles [not found] ` <CGME20261113104832epcas5p4e1e9a3dedeb0c9c60cb80c23eb5d930d@epcas5p4.samsung.com> @ 2026-11-13 11:05 ` Raghav Sharma 2026-11-13 10:57 ` Peter Griffin 0 siblings, 1 reply; 21+ messages in thread From: Raghav Sharma @ 2026-11-13 11:05 UTC (permalink / raw) To: krzk, s.nawrocki, cw00.choi, peter.griffin, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, raghav.s Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy From: Alim Akhtar <alim.akhtar@samsung.com> Add exynos8855 sysreg compatibles in bindings Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Raghav Sharma <raghav.s@samsung.com> --- .../bindings/soc/samsung/samsung,exynos-sysreg.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml index fcdb9ffd2644..845e0caba15a 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -31,6 +31,10 @@ properties: - samsung,exynos5-sysreg - samsung,exynos7870-cam0-sysreg - samsung,exynos7870-disp-sysreg + - samsung,exynos8855-hsi-sysreg + - samsung,exynos8855-peric-sysreg + - samsung,exynos8855-peris-sysreg + - samsung,exynos8855-usb-sysreg - samsung,exynos8895-fsys0-sysreg - samsung,exynos8895-fsys1-sysreg - samsung,exynos8895-peric0-sysreg @@ -103,6 +107,10 @@ allOf: - samsung,exynos850-cmgp-sysreg - samsung,exynos850-peri-sysreg - samsung,exynos850-sysreg + - samsung,exynos8855-hsi-sysreg + - samsung,exynos8855-peric-sysreg + - samsung,exynos8855-peris-sysreg + - samsung,exynos8855-usb-sysreg - samsung,exynos8895-fsys0-sysreg - samsung,exynos8895-fsys1-sysreg - samsung,exynos8895-peric0-sysreg -- 2.34.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 01/14 RESEND] dt-bindings: soc: samsung: Exynos8855 SYSREG compatibles 2026-11-13 11:05 ` [PATCH v3 01/14 RESEND] dt-bindings: soc: samsung: Exynos8855 SYSREG compatibles Raghav Sharma @ 2026-11-13 10:57 ` Peter Griffin 0 siblings, 0 replies; 21+ messages in thread From: Peter Griffin @ 2026-11-13 10:57 UTC (permalink / raw) To: Raghav Sharma Cc: krzk, s.nawrocki, cw00.choi, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy On Fri, 13 Nov 2026 at 10:53, Raghav Sharma <raghav.s@samsung.com> wrote: > > From: Alim Akhtar <alim.akhtar@samsung.com> > > Add exynos8855 sysreg compatibles in bindings > > Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> > Signed-off-by: Raghav Sharma <raghav.s@samsung.com> > --- Reviewed-by: Peter Griffin <peter.griffin@linaro.org> > .../bindings/soc/samsung/samsung,exynos-sysreg.yaml | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml > index fcdb9ffd2644..845e0caba15a 100644 > --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml > +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml > @@ -31,6 +31,10 @@ properties: > - samsung,exynos5-sysreg > - samsung,exynos7870-cam0-sysreg > - samsung,exynos7870-disp-sysreg > + - samsung,exynos8855-hsi-sysreg > + - samsung,exynos8855-peric-sysreg > + - samsung,exynos8855-peris-sysreg > + - samsung,exynos8855-usb-sysreg > - samsung,exynos8895-fsys0-sysreg > - samsung,exynos8895-fsys1-sysreg > - samsung,exynos8895-peric0-sysreg > @@ -103,6 +107,10 @@ allOf: > - samsung,exynos850-cmgp-sysreg > - samsung,exynos850-peri-sysreg > - samsung,exynos850-sysreg > + - samsung,exynos8855-hsi-sysreg > + - samsung,exynos8855-peric-sysreg > + - samsung,exynos8855-peris-sysreg > + - samsung,exynos8855-usb-sysreg > - samsung,exynos8895-fsys0-sysreg > - samsung,exynos8895-fsys1-sysreg > - samsung,exynos8895-peric0-sysreg > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <CGME20261113104835epcas5p4771d9933265138321769ebe010ee7334@epcas5p4.samsung.com>]
* [PATCH v3 02/14 RESEND] dt-bindings: clock: exynos8855: add top & peric clock definitions [not found] ` <CGME20261113104835epcas5p4771d9933265138321769ebe010ee7334@epcas5p4.samsung.com> @ 2026-11-13 11:06 ` Raghav Sharma 2026-11-13 11:01 ` Peter Griffin 0 siblings, 1 reply; 21+ messages in thread From: Raghav Sharma @ 2026-11-13 11:06 UTC (permalink / raw) To: krzk, s.nawrocki, cw00.choi, peter.griffin, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, raghav.s Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy, Krzysztof Kozlowski Add device tree clock binding definitions for CMU_TOP & CMU_PERIC Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Raghav Sharma <raghav.s@samsung.com> --- .../clock/samsung,exynos8855-clock.yaml | 133 +++++++++++ .../dt-bindings/clock/samsung,exynos8855.h | 206 ++++++++++++++++++ 2 files changed, 339 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml create mode 100644 include/dt-bindings/clock/samsung,exynos8855.h diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml new file mode 100644 index 000000000000..486b7347ad44 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos8855-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos 8855 SoC clock controller + +maintainers: + - Raghav Sharma <raghav.s@samsung.com> + +description: | + Exynos 8855 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. Root clocks in that clock tree are + two external clocks:: OSCCLK/XTCXO (76.8 MHz) and RTCCLK/XrtcXTI (32768 Hz). + The external OSCCLK must be defined as fixed-rate clock in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other clocks of function blocks (other CMUs) are usually + derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/samsung,exynos8855.h' header. + +properties: + compatible: + enum: + - samsung,exynos8855-cmu-peric + - samsung,exynos8855-cmu-top + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + + samsung,sysreg: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to system registers interface. + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos8855-cmu-peric + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_PERIC NOC clock (from CMU_TOP) + - description: CMU_PERIC MMC_CARD clock (from CMU_TOP) + - description: CMU_PERIC IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: mmc_card + - const: ip + + - if: + properties: + compatible: + contains: + const: samsung,exynos8855-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos8855-cmu-top + then: + properties: + samsung,sysreg: false + else: + required: + - samsung,sysreg + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/samsung,exynos8855.h> + + cmu_peric0: clock-controller@15400000 { + compatible = "samsung,exynos8855-cmu-peric"; + reg = <0x15400000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top CLKCMU_DOUT_PERIC_NOC>, + <&cmu_top CLKCMU_DOUT_PERIC_MMC_CARD>, + <&cmu_top CLKCMU_DOUT_PERIC_IP>; + clock-names = "oscclk", + "bus", + "mmc_card", + "ip"; + samsung,sysreg = <&sysreg_peric>; + }; + +... diff --git a/include/dt-bindings/clock/samsung,exynos8855.h b/include/dt-bindings/clock/samsung,exynos8855.h new file mode 100644 index 000000000000..cd445bb45070 --- /dev/null +++ b/include/dt-bindings/clock/samsung,exynos8855.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2026 Samsung Electronics Co., Ltd. + * Author: Raghav Sharma <raghav.s@samsung.com> + * + * Device Tree binding constants for Exynos 8855 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS8855_H +#define _DT_BINDINGS_CLOCK_EXYNOS8855_H + +/* CMU_TOP */ +#define FOUT_SHARED0_PLL 1 +#define FOUT_SHARED1_PLL 2 +#define FOUT_SHARED2_PLL 3 +#define FOUT_SHARED3_PLL 4 +#define FOUT_SHARED4_PLL 5 +#define FOUT_MMC_PLL 6 +#define MOUT_SHARED0_PLL 7 +#define MOUT_SHARED1_PLL 8 +#define MOUT_SHARED2_PLL 9 +#define MOUT_SHARED3_PLL 10 +#define MOUT_SHARED4_PLL 11 +#define MOUT_MMC_PLL 12 +#define CLKCMU_MOUT_PERIC_NOC 13 +#define CLKCMU_MOUT_PERIC_MMC_CARD 14 +#define CLKCMU_MOUT_PERIC_IP 15 +#define CLKCMU_DOUT_PERIC_NOC 16 +#define CLKCMU_DOUT_PERIC_MMC_CARD 17 +#define CLKCMU_DOUT_PERIC_IP 18 +#define DOUT_SHARED0_DIV1 19 +#define DOUT_SHARED0_DIV2 20 +#define DOUT_SHARED0_DIV3 21 +#define DOUT_SHARED0_DIV4 22 +#define DOUT_SHARED1_DIV1 23 +#define DOUT_SHARED1_DIV2 24 +#define DOUT_SHARED1_DIV3 25 +#define DOUT_SHARED1_DIV4 26 +#define DOUT_SHARED2_DIV1 27 +#define DOUT_SHARED2_DIV2 28 +#define DOUT_SHARED2_DIV3 29 +#define DOUT_SHARED2_DIV4 30 +#define DOUT_SHARED3_DIV1 31 +#define DOUT_SHARED3_DIV2 32 +#define DOUT_SHARED3_DIV3 33 +#define DOUT_SHARED3_DIV4 34 +#define DOUT_SHARED4_DIV1 35 +#define DOUT_SHARED4_DIV2 36 +#define DOUT_SHARED4_DIV3 37 +#define DOUT_SHARED4_DIV4 38 +#define FOUT_MMC_PLL_DIV1 39 +#define FOUT_MMC_PLL_DIV2 40 +#define CLKCMU_MOUT_PERIS_GIC 41 +#define CLKCMU_MOUT_PERIS_NOC 42 +#define CLKCMU_DOUT_PERIS_GIC 43 +#define CLKCMU_DOUT_PERIS_NOC 44 +#define FOUT_MMC_PLL_CLKOUT_DIV2 45 +#define CLKCMU_MOUT_HSI_NOC 46 +#define CLKCMU_MOUT_HSI_UFS_EMBD 47 +#define CLKCMU_DOUT_HSI_NOC 48 +#define CLKCMU_DOUT_HSI_UFS_EMBD 49 +#define CLKCMU_MOUT_USB_NOC 50 +#define CLKCMU_MOUT_USB_USB20DRD 51 +#define CLKCMU_DOUT_USB_NOC 52 +#define CLKCMU_DOUT_USB_USB20DRD 53 +#define FOUT_MIF_SWITCH_PLL 54 +#define MOUT_MIF_SWITCH_PLL 55 +#define FOUT_MMC_PLL_DIV3 56 +#define FOUT_MMC_PLL_DIV4 57 +#define FOUT_MIF_SWITCH_PLL_DIV1 58 +#define FOUT_MIF_SWITCH_PLL_DIV2 59 +#define FOUT_MIF_SWITCH_PLL_DIV3 60 +#define FOUT_MIF_SWITCH_PLL_DIV4 61 +#define CLKCMU_MOUT_AUD_CPU 62 +#define CLKCMU_MOUT_AUD_NOC 63 +#define CLKCMU_MOUT_CPUCL0_SWITCH 64 +#define CLKCMU_MOUT_CPUCL0_NOCP 65 +#define CLKCMU_MOUT_DSU_SWITCH 66 +#define CLKCMU_MOUT_CPUCL1_SWITCH 67 +#define CLKCMU_MOUT_CIS_CLK0 68 +#define CLKCMU_MOUT_CIS_CLK1 69 +#define CLKCMU_MOUT_CIS_CLK2 70 +#define CLKCMU_MOUT_CIS_CLK3 71 +#define CLKCMU_MOUT_CIS_CLK4 72 +#define CLKCMU_MOUT_CMU_BOOST_TOP 73 +#define CLKCMU_MOUT_CMU_BOOST 74 +#define CLKCMU_MOUT_CMU_BOOST_CPU 75 +#define CLKCMU_MOUT_CMU_BOOST_MIF0 76 +#define CLKCMU_MOUT_CSIS_NOC 77 +#define CLKCMU_MOUT_CSTAT_NOC 78 +#define CLKCMU_MOUT_CSTAT_BYRP 79 +#define CLKCMU_MOUT_DPU_NOC 80 +#define CLKCMU_MOUT_G3DCORE_SWITCH 81 +#define CLKCMU_MOUT_M2M_NOC 82 +#define CLKCMU_MOUT_M2M_JPEG 83 +#define CLKCMU_MOUT_M2M_GDC 84 +#define CLKCMU_MOUT_MIF1_NOCP 85 +#define CLKCMU_MOUT_MFC_NOC 86 +#define CLKCMU_MOUT_MIF0_NOCP 87 +#define CLKCMU_MOUT_NOCL0_NOC 88 +#define CLKCMU_MOUT_NOCL1A_NOC 89 +#define CLKCMU_MOUT_RGBP_NOC 90 +#define CLKCMU_MOUT_YUVP_NOC 91 +#define CLKCMU_MOUT_ALIVE_NOC 92 +#define CLKCMU_MOUT_CSIS_DCPHY 93 +#define CLKCMU_MOUT_CSIS_OIS 94 +#define CLKCMU_MOUT_ICPU_NOCD_0 95 +#define CLKCMU_MOUT_ICPU_NOCD_1 96 +#define CLKCMU_MOUT_GNPU0_NOC 97 +#define CLKCMU_MOUT_GNPU0_XMAA 98 +#define CLKCMU_MOUT_SDMA_NOC 99 +#define CLKCMU_MOUT_DNC_HTU 100 +#define CLKCMU_MOUT_DNC_NOC 101 +#define CLKCMU_MOUT_PSP_NOC 102 +#define CLKCMU_MOUT_G3D_NOCP 103 +#define CLKCMU_MOUT_USI_NOC 104 +#define CLKCMU_MOUT_USI_IP 105 +#define CLKCMU_MOUT_CPUCL0_DBG_NOC 106 +#define CLKCMU_MOUT_BOOST_RCO 107 +#define CLKCMU_MOUT_MIF0_SWITCH 108 +#define CLKCMU_MOUT_MIF1_SWITCH 109 +#define CLKCMU_MOUT_NOCL1B_NOC 110 +#define CLKCMU_MOUT_CPUCL2_SWITCH 111 +#define CLKCMU_MOUT_CMU_BOOST_MIF1 112 +#define CLKCMU_MOUT_CSTAT_MCSC 113 +#define CLKCMU_MOUT_G3D_HTU 114 +#define CLKCMU_DOUT_AUD_CPU 115 +#define CLKCMU_DOUT_AUD_NOC 116 +#define CLKCMU_DOUT_CPUCL0_SWITCH 117 +#define CLKCMU_DOUT_CPUCL0_NOCP 118 +#define CLKCMU_DOUT_DSU_SWITCH 119 +#define CLKCMU_DOUT_CPUCL1_SWITCH 120 +#define CLKCMU_DOUT_CIS_CLK0 121 +#define CLKCMU_DOUT_CIS_CLK1 122 +#define CLKCMU_DOUT_CIS_CLK2 123 +#define CLKCMU_DOUT_CIS_CLK3 124 +#define CLKCMU_DOUT_CIS_CLK4 125 +#define CLKCMU_DOUT_CMU_BOOST_TOP 126 +#define CLKCMU_DOUT_CMU_BOOST 127 +#define CLKCMU_DOUT_CMU_BOOST_CPU 128 +#define CLKCMU_DOUT_CMU_BOOST_MIF0 129 +#define CLKCMU_DOUT_CSIS_NOC 130 +#define CLKCMU_DOUT_CSTAT_NOC 131 +#define CLKCMU_DOUT_CSTAT_BYRP 132 +#define CLKCMU_DOUT_DPU_NOC 133 +#define CLKCMU_DOUT_G3DCORE_SWITCH 134 +#define CLKCMU_DOUT_M2M_NOC 135 +#define CLKCMU_DOUT_M2M_JPEG 136 +#define CLKCMU_DOUT_M2M_GDC 137 +#define CLKCMU_DOUT_MIF1_NOCP 138 +#define CLKCMU_DOUT_MFC_NOC 139 +#define CLKCMU_DOUT_MIF0_NOCP 140 +#define CLKCMU_DOUT_NOCL0_NOC 141 +#define CLKCMU_DOUT_NOCL1A_NOC 142 +#define CLKCMU_DOUT_RGBP_NOC 143 +#define CLKCMU_DOUT_YUVP_NOC 144 +#define CLKCMU_DOUT_ALIVE_NOC 145 +#define CLKCMU_DOUT_CSIS_DCPHY 146 +#define CLKCMU_DOUT_CSIS_OIS 147 +#define CLKCMU_DOUT_ICPU_NOCD_0 148 +#define CLKCMU_DOUT_ICPU_NOCD_1 149 +#define CLKCMU_DOUT_GNPU0_NOC 150 +#define CLKCMU_DOUT_GNPU0_XMAA 151 +#define CLKCMU_DOUT_SDMA_NOC 152 +#define CLKCMU_DOUT_DNC_HTU 153 +#define CLKCMU_DOUT_DNC_NOC 154 +#define CLKCMU_DOUT_PSP_NOC 155 +#define CLKCMU_DOUT_G3D_NOCP 156 +#define CLKCMU_DOUT_USI_NOC 157 +#define CLKCMU_DOUT_USI_IP 158 +#define CLKCMU_DOUT_CPUCL0_DBG_NOC 159 +#define CLKCMU_DOUT_NOCL1B_NOC 160 +#define CLKCMU_DOUT_CPUCL2_SWITCH 161 +#define CLKCMU_DOUT_CMU_BOOST_MIF1 162 +#define CLKCMU_DOUT_CSTAT_MCSC 163 +#define CLKCMU_DOUT_G3D_HTU 164 + +/* CMU_PERIC */ +#define CLK_MOUT_PERIC_IP_USER 1 +#define CLK_MOUT_PERIC_MMC_CARD_USER 2 +#define CLK_MOUT_PERIC_NOC_USER 3 +#define CLK_MOUT_PERIC_I2C 4 +#define CLK_MOUT_PERIC_UART_DBG 5 +#define CLK_MOUT_PERIC_USI00 6 +#define CLK_MOUT_PERIC_USI01 7 +#define CLK_MOUT_PERIC_USI02 8 +#define CLK_MOUT_PERIC_USI03 9 +#define CLK_MOUT_PERIC_USI04 10 +#define CLK_MOUT_PERIC_USI09_USI_OIS 11 +#define CLK_MOUT_PERIC_USI10_USI_OIS 12 +#define CLK_DOUT_PERIC_NOCP 13 +#define CLK_DOUT_PERIC_UART_DBG 14 +#define CLK_DOUT_PERIC_USI00_USI 15 +#define CLK_DOUT_PERIC_USI01_USI 16 +#define CLK_DOUT_PERIC_USI02_USI 17 +#define CLK_DOUT_PERIC_USI03_USI 18 +#define CLK_DOUT_PERIC_USI04_USI 19 +#define CLK_DOUT_PERIC_USI09_USI_OIS 20 +#define CLK_DOUT_PERIC_USI10_USI_OIS 21 +#define CLK_DOUT_PERIC_USI_I2C 22 +#define CLK_GOUT_CMU_PERIC 23 +#define CLK_GOUT_SYSREG_PERIC 24 +#define CLK_GOUT_UART_DBG_PERIC 25 +#define CLK_GOUT_USI_PERIC 26 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS8855_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 02/14 RESEND] dt-bindings: clock: exynos8855: add top & peric clock definitions 2026-11-13 11:06 ` [PATCH v3 02/14 RESEND] dt-bindings: clock: exynos8855: add top & peric clock definitions Raghav Sharma @ 2026-11-13 11:01 ` Peter Griffin 0 siblings, 0 replies; 21+ messages in thread From: Peter Griffin @ 2026-11-13 11:01 UTC (permalink / raw) To: Raghav Sharma Cc: krzk, s.nawrocki, cw00.choi, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy, Krzysztof Kozlowski On Fri, 13 Nov 2026 at 10:58, Raghav Sharma <raghav.s@samsung.com> wrote: > > Add device tree clock binding definitions for CMU_TOP & CMU_PERIC > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> > Signed-off-by: Raghav Sharma <raghav.s@samsung.com> > --- Reviewed-by: Peter Griffin <peter.griffin@linaro.org> > .../clock/samsung,exynos8855-clock.yaml | 133 +++++++++++ > .../dt-bindings/clock/samsung,exynos8855.h | 206 ++++++++++++++++++ > 2 files changed, 339 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml > create mode 100644 include/dt-bindings/clock/samsung,exynos8855.h > > diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml > new file mode 100644 > index 000000000000..486b7347ad44 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml > @@ -0,0 +1,133 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/samsung,exynos8855-clock.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Samsung Exynos 8855 SoC clock controller > + > +maintainers: > + - Raghav Sharma <raghav.s@samsung.com> > + > +description: | > + Exynos 8855 clock controller is comprised of several CMU units, generating > + clocks for different domains. Those CMU units are modeled as separate device > + tree nodes, and might depend on each other. Root clocks in that clock tree are > + two external clocks:: OSCCLK/XTCXO (76.8 MHz) and RTCCLK/XrtcXTI (32768 Hz). > + The external OSCCLK must be defined as fixed-rate clock in dts. > + > + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and > + dividers; all other clocks of function blocks (other CMUs) are usually > + derived from CMU_TOP. > + > + Each clock is assigned an identifier and client nodes can use this identifier > + to specify the clock which they consume. All clocks available for usage > + in clock consumer nodes are defined as preprocessor macros in > + 'include/dt-bindings/clock/samsung,exynos8855.h' header. > + > +properties: > + compatible: > + enum: > + - samsung,exynos8855-cmu-peric > + - samsung,exynos8855-cmu-top > + > + clocks: > + minItems: 1 > + maxItems: 4 > + > + clock-names: > + minItems: 1 > + maxItems: 4 > + > + "#clock-cells": > + const: 1 > + > + reg: > + maxItems: 1 > + > + samsung,sysreg: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to system registers interface. > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: samsung,exynos8855-cmu-peric > + > + then: > + properties: > + clocks: > + items: > + - description: External reference clock (76.8 MHz) > + - description: CMU_PERIC NOC clock (from CMU_TOP) > + - description: CMU_PERIC MMC_CARD clock (from CMU_TOP) > + - description: CMU_PERIC IP clock (from CMU_TOP) > + > + clock-names: > + items: > + - const: oscclk > + - const: bus > + - const: mmc_card > + - const: ip > + > + - if: > + properties: > + compatible: > + contains: > + const: samsung,exynos8855-cmu-top > + > + then: > + properties: > + clocks: > + items: > + - description: External reference clock (76.8 MHz) > + > + clock-names: > + items: > + - const: oscclk > + > + - if: > + properties: > + compatible: > + contains: > + const: samsung,exynos8855-cmu-top > + then: > + properties: > + samsung,sysreg: false > + else: > + required: > + - samsung,sysreg > + > +required: > + - compatible > + - "#clock-cells" > + - clocks > + - clock-names > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/samsung,exynos8855.h> > + > + cmu_peric0: clock-controller@15400000 { > + compatible = "samsung,exynos8855-cmu-peric"; > + reg = <0x15400000 0x8000>; > + #clock-cells = <1>; > + > + clocks = <&xtcxo>, > + <&cmu_top CLKCMU_DOUT_PERIC_NOC>, > + <&cmu_top CLKCMU_DOUT_PERIC_MMC_CARD>, > + <&cmu_top CLKCMU_DOUT_PERIC_IP>; > + clock-names = "oscclk", > + "bus", > + "mmc_card", > + "ip"; > + samsung,sysreg = <&sysreg_peric>; > + }; > + > +... > diff --git a/include/dt-bindings/clock/samsung,exynos8855.h b/include/dt-bindings/clock/samsung,exynos8855.h > new file mode 100644 > index 000000000000..cd445bb45070 > --- /dev/null > +++ b/include/dt-bindings/clock/samsung,exynos8855.h > @@ -0,0 +1,206 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2026 Samsung Electronics Co., Ltd. > + * Author: Raghav Sharma <raghav.s@samsung.com> > + * > + * Device Tree binding constants for Exynos 8855 clock controller. > + */ > + > +#ifndef _DT_BINDINGS_CLOCK_EXYNOS8855_H > +#define _DT_BINDINGS_CLOCK_EXYNOS8855_H > + > +/* CMU_TOP */ > +#define FOUT_SHARED0_PLL 1 > +#define FOUT_SHARED1_PLL 2 > +#define FOUT_SHARED2_PLL 3 > +#define FOUT_SHARED3_PLL 4 > +#define FOUT_SHARED4_PLL 5 > +#define FOUT_MMC_PLL 6 > +#define MOUT_SHARED0_PLL 7 > +#define MOUT_SHARED1_PLL 8 > +#define MOUT_SHARED2_PLL 9 > +#define MOUT_SHARED3_PLL 10 > +#define MOUT_SHARED4_PLL 11 > +#define MOUT_MMC_PLL 12 > +#define CLKCMU_MOUT_PERIC_NOC 13 > +#define CLKCMU_MOUT_PERIC_MMC_CARD 14 > +#define CLKCMU_MOUT_PERIC_IP 15 > +#define CLKCMU_DOUT_PERIC_NOC 16 > +#define CLKCMU_DOUT_PERIC_MMC_CARD 17 > +#define CLKCMU_DOUT_PERIC_IP 18 > +#define DOUT_SHARED0_DIV1 19 > +#define DOUT_SHARED0_DIV2 20 > +#define DOUT_SHARED0_DIV3 21 > +#define DOUT_SHARED0_DIV4 22 > +#define DOUT_SHARED1_DIV1 23 > +#define DOUT_SHARED1_DIV2 24 > +#define DOUT_SHARED1_DIV3 25 > +#define DOUT_SHARED1_DIV4 26 > +#define DOUT_SHARED2_DIV1 27 > +#define DOUT_SHARED2_DIV2 28 > +#define DOUT_SHARED2_DIV3 29 > +#define DOUT_SHARED2_DIV4 30 > +#define DOUT_SHARED3_DIV1 31 > +#define DOUT_SHARED3_DIV2 32 > +#define DOUT_SHARED3_DIV3 33 > +#define DOUT_SHARED3_DIV4 34 > +#define DOUT_SHARED4_DIV1 35 > +#define DOUT_SHARED4_DIV2 36 > +#define DOUT_SHARED4_DIV3 37 > +#define DOUT_SHARED4_DIV4 38 > +#define FOUT_MMC_PLL_DIV1 39 > +#define FOUT_MMC_PLL_DIV2 40 > +#define CLKCMU_MOUT_PERIS_GIC 41 > +#define CLKCMU_MOUT_PERIS_NOC 42 > +#define CLKCMU_DOUT_PERIS_GIC 43 > +#define CLKCMU_DOUT_PERIS_NOC 44 > +#define FOUT_MMC_PLL_CLKOUT_DIV2 45 > +#define CLKCMU_MOUT_HSI_NOC 46 > +#define CLKCMU_MOUT_HSI_UFS_EMBD 47 > +#define CLKCMU_DOUT_HSI_NOC 48 > +#define CLKCMU_DOUT_HSI_UFS_EMBD 49 > +#define CLKCMU_MOUT_USB_NOC 50 > +#define CLKCMU_MOUT_USB_USB20DRD 51 > +#define CLKCMU_DOUT_USB_NOC 52 > +#define CLKCMU_DOUT_USB_USB20DRD 53 > +#define FOUT_MIF_SWITCH_PLL 54 > +#define MOUT_MIF_SWITCH_PLL 55 > +#define FOUT_MMC_PLL_DIV3 56 > +#define FOUT_MMC_PLL_DIV4 57 > +#define FOUT_MIF_SWITCH_PLL_DIV1 58 > +#define FOUT_MIF_SWITCH_PLL_DIV2 59 > +#define FOUT_MIF_SWITCH_PLL_DIV3 60 > +#define FOUT_MIF_SWITCH_PLL_DIV4 61 > +#define CLKCMU_MOUT_AUD_CPU 62 > +#define CLKCMU_MOUT_AUD_NOC 63 > +#define CLKCMU_MOUT_CPUCL0_SWITCH 64 > +#define CLKCMU_MOUT_CPUCL0_NOCP 65 > +#define CLKCMU_MOUT_DSU_SWITCH 66 > +#define CLKCMU_MOUT_CPUCL1_SWITCH 67 > +#define CLKCMU_MOUT_CIS_CLK0 68 > +#define CLKCMU_MOUT_CIS_CLK1 69 > +#define CLKCMU_MOUT_CIS_CLK2 70 > +#define CLKCMU_MOUT_CIS_CLK3 71 > +#define CLKCMU_MOUT_CIS_CLK4 72 > +#define CLKCMU_MOUT_CMU_BOOST_TOP 73 > +#define CLKCMU_MOUT_CMU_BOOST 74 > +#define CLKCMU_MOUT_CMU_BOOST_CPU 75 > +#define CLKCMU_MOUT_CMU_BOOST_MIF0 76 > +#define CLKCMU_MOUT_CSIS_NOC 77 > +#define CLKCMU_MOUT_CSTAT_NOC 78 > +#define CLKCMU_MOUT_CSTAT_BYRP 79 > +#define CLKCMU_MOUT_DPU_NOC 80 > +#define CLKCMU_MOUT_G3DCORE_SWITCH 81 > +#define CLKCMU_MOUT_M2M_NOC 82 > +#define CLKCMU_MOUT_M2M_JPEG 83 > +#define CLKCMU_MOUT_M2M_GDC 84 > +#define CLKCMU_MOUT_MIF1_NOCP 85 > +#define CLKCMU_MOUT_MFC_NOC 86 > +#define CLKCMU_MOUT_MIF0_NOCP 87 > +#define CLKCMU_MOUT_NOCL0_NOC 88 > +#define CLKCMU_MOUT_NOCL1A_NOC 89 > +#define CLKCMU_MOUT_RGBP_NOC 90 > +#define CLKCMU_MOUT_YUVP_NOC 91 > +#define CLKCMU_MOUT_ALIVE_NOC 92 > +#define CLKCMU_MOUT_CSIS_DCPHY 93 > +#define CLKCMU_MOUT_CSIS_OIS 94 > +#define CLKCMU_MOUT_ICPU_NOCD_0 95 > +#define CLKCMU_MOUT_ICPU_NOCD_1 96 > +#define CLKCMU_MOUT_GNPU0_NOC 97 > +#define CLKCMU_MOUT_GNPU0_XMAA 98 > +#define CLKCMU_MOUT_SDMA_NOC 99 > +#define CLKCMU_MOUT_DNC_HTU 100 > +#define CLKCMU_MOUT_DNC_NOC 101 > +#define CLKCMU_MOUT_PSP_NOC 102 > +#define CLKCMU_MOUT_G3D_NOCP 103 > +#define CLKCMU_MOUT_USI_NOC 104 > +#define CLKCMU_MOUT_USI_IP 105 > +#define CLKCMU_MOUT_CPUCL0_DBG_NOC 106 > +#define CLKCMU_MOUT_BOOST_RCO 107 > +#define CLKCMU_MOUT_MIF0_SWITCH 108 > +#define CLKCMU_MOUT_MIF1_SWITCH 109 > +#define CLKCMU_MOUT_NOCL1B_NOC 110 > +#define CLKCMU_MOUT_CPUCL2_SWITCH 111 > +#define CLKCMU_MOUT_CMU_BOOST_MIF1 112 > +#define CLKCMU_MOUT_CSTAT_MCSC 113 > +#define CLKCMU_MOUT_G3D_HTU 114 > +#define CLKCMU_DOUT_AUD_CPU 115 > +#define CLKCMU_DOUT_AUD_NOC 116 > +#define CLKCMU_DOUT_CPUCL0_SWITCH 117 > +#define CLKCMU_DOUT_CPUCL0_NOCP 118 > +#define CLKCMU_DOUT_DSU_SWITCH 119 > +#define CLKCMU_DOUT_CPUCL1_SWITCH 120 > +#define CLKCMU_DOUT_CIS_CLK0 121 > +#define CLKCMU_DOUT_CIS_CLK1 122 > +#define CLKCMU_DOUT_CIS_CLK2 123 > +#define CLKCMU_DOUT_CIS_CLK3 124 > +#define CLKCMU_DOUT_CIS_CLK4 125 > +#define CLKCMU_DOUT_CMU_BOOST_TOP 126 > +#define CLKCMU_DOUT_CMU_BOOST 127 > +#define CLKCMU_DOUT_CMU_BOOST_CPU 128 > +#define CLKCMU_DOUT_CMU_BOOST_MIF0 129 > +#define CLKCMU_DOUT_CSIS_NOC 130 > +#define CLKCMU_DOUT_CSTAT_NOC 131 > +#define CLKCMU_DOUT_CSTAT_BYRP 132 > +#define CLKCMU_DOUT_DPU_NOC 133 > +#define CLKCMU_DOUT_G3DCORE_SWITCH 134 > +#define CLKCMU_DOUT_M2M_NOC 135 > +#define CLKCMU_DOUT_M2M_JPEG 136 > +#define CLKCMU_DOUT_M2M_GDC 137 > +#define CLKCMU_DOUT_MIF1_NOCP 138 > +#define CLKCMU_DOUT_MFC_NOC 139 > +#define CLKCMU_DOUT_MIF0_NOCP 140 > +#define CLKCMU_DOUT_NOCL0_NOC 141 > +#define CLKCMU_DOUT_NOCL1A_NOC 142 > +#define CLKCMU_DOUT_RGBP_NOC 143 > +#define CLKCMU_DOUT_YUVP_NOC 144 > +#define CLKCMU_DOUT_ALIVE_NOC 145 > +#define CLKCMU_DOUT_CSIS_DCPHY 146 > +#define CLKCMU_DOUT_CSIS_OIS 147 > +#define CLKCMU_DOUT_ICPU_NOCD_0 148 > +#define CLKCMU_DOUT_ICPU_NOCD_1 149 > +#define CLKCMU_DOUT_GNPU0_NOC 150 > +#define CLKCMU_DOUT_GNPU0_XMAA 151 > +#define CLKCMU_DOUT_SDMA_NOC 152 > +#define CLKCMU_DOUT_DNC_HTU 153 > +#define CLKCMU_DOUT_DNC_NOC 154 > +#define CLKCMU_DOUT_PSP_NOC 155 > +#define CLKCMU_DOUT_G3D_NOCP 156 > +#define CLKCMU_DOUT_USI_NOC 157 > +#define CLKCMU_DOUT_USI_IP 158 > +#define CLKCMU_DOUT_CPUCL0_DBG_NOC 159 > +#define CLKCMU_DOUT_NOCL1B_NOC 160 > +#define CLKCMU_DOUT_CPUCL2_SWITCH 161 > +#define CLKCMU_DOUT_CMU_BOOST_MIF1 162 > +#define CLKCMU_DOUT_CSTAT_MCSC 163 > +#define CLKCMU_DOUT_G3D_HTU 164 > + > +/* CMU_PERIC */ > +#define CLK_MOUT_PERIC_IP_USER 1 > +#define CLK_MOUT_PERIC_MMC_CARD_USER 2 > +#define CLK_MOUT_PERIC_NOC_USER 3 > +#define CLK_MOUT_PERIC_I2C 4 > +#define CLK_MOUT_PERIC_UART_DBG 5 > +#define CLK_MOUT_PERIC_USI00 6 > +#define CLK_MOUT_PERIC_USI01 7 > +#define CLK_MOUT_PERIC_USI02 8 > +#define CLK_MOUT_PERIC_USI03 9 > +#define CLK_MOUT_PERIC_USI04 10 > +#define CLK_MOUT_PERIC_USI09_USI_OIS 11 > +#define CLK_MOUT_PERIC_USI10_USI_OIS 12 > +#define CLK_DOUT_PERIC_NOCP 13 > +#define CLK_DOUT_PERIC_UART_DBG 14 > +#define CLK_DOUT_PERIC_USI00_USI 15 > +#define CLK_DOUT_PERIC_USI01_USI 16 > +#define CLK_DOUT_PERIC_USI02_USI 17 > +#define CLK_DOUT_PERIC_USI03_USI 18 > +#define CLK_DOUT_PERIC_USI04_USI 19 > +#define CLK_DOUT_PERIC_USI09_USI_OIS 20 > +#define CLK_DOUT_PERIC_USI10_USI_OIS 21 > +#define CLK_DOUT_PERIC_USI_I2C 22 > +#define CLK_GOUT_CMU_PERIC 23 > +#define CLK_GOUT_SYSREG_PERIC 24 > +#define CLK_GOUT_UART_DBG_PERIC 25 > +#define CLK_GOUT_USI_PERIC 26 > + > +#endif /* _DT_BINDINGS_CLOCK_EXYNOS8855_H */ > -- > 2.34.1 > > ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <CGME20261113104838epcas5p2623c7a05b6163954e13e98367063e7d4@epcas5p2.samsung.com>]
* [PATCH v3 03/14 RESEND] dt-bindings: clock: exynos8855: add peris clock definitions [not found] ` <CGME20261113104838epcas5p2623c7a05b6163954e13e98367063e7d4@epcas5p2.samsung.com> @ 2026-11-13 11:06 ` Raghav Sharma 2026-11-13 11:25 ` Peter Griffin 0 siblings, 1 reply; 21+ messages in thread From: Raghav Sharma @ 2026-11-13 11:06 UTC (permalink / raw) To: krzk, s.nawrocki, cw00.choi, peter.griffin, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, raghav.s Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy, Krzysztof Kozlowski Add device tree clock binding definitions for CMU_PERIS Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Raghav Sharma <raghav.s@samsung.com> --- .../clock/samsung,exynos8855-clock.yaml | 21 +++++++++++++++++++ .../dt-bindings/clock/samsung,exynos8855.h | 11 ++++++++++ 2 files changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml index 486b7347ad44..53fc8040e173 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml @@ -29,6 +29,7 @@ properties: compatible: enum: - samsung,exynos8855-cmu-peric + - samsung,exynos8855-cmu-peris - samsung,exynos8855-cmu-top clocks: @@ -73,6 +74,26 @@ allOf: - const: mmc_card - const: ip + - if: + properties: + compatible: + contains: + const: samsung,exynos8855-cmu-peris + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_PERIS GIC clock (from CMU_TOP) + - description: CMU_PERIS NOC clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: gic + - const: bus + - if: properties: compatible: diff --git a/include/dt-bindings/clock/samsung,exynos8855.h b/include/dt-bindings/clock/samsung,exynos8855.h index cd445bb45070..5d8b38a744b5 100644 --- a/include/dt-bindings/clock/samsung,exynos8855.h +++ b/include/dt-bindings/clock/samsung,exynos8855.h @@ -203,4 +203,15 @@ #define CLK_GOUT_UART_DBG_PERIC 25 #define CLK_GOUT_USI_PERIC 26 +/* CMU_PERIS */ +#define CLK_MOUT_PERIS_NOC_USER 1 +#define CLK_MOUT_PERIS_GIC 2 +#define CLK_MOUT_PERIS_GIC_USER 3 +#define CLK_DOUT_PERIS_NOCP 4 +#define CLK_DOUT_PERIS_OTP 5 +#define CLK_GOUT_CMU_PERIS 6 +#define CLK_GOUT_SYSREG_PERIS 7 +#define CLK_GOUT_WDT0_PERIS 8 +#define CLK_GOUT_WDT1_PERIS 9 + #endif /* _DT_BINDINGS_CLOCK_EXYNOS8855_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 03/14 RESEND] dt-bindings: clock: exynos8855: add peris clock definitions 2026-11-13 11:06 ` [PATCH v3 03/14 RESEND] dt-bindings: clock: exynos8855: add peris " Raghav Sharma @ 2026-11-13 11:25 ` Peter Griffin 0 siblings, 0 replies; 21+ messages in thread From: Peter Griffin @ 2026-11-13 11:25 UTC (permalink / raw) To: Raghav Sharma Cc: krzk, s.nawrocki, cw00.choi, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy, Krzysztof Kozlowski On Fri, 13 Nov 2026 at 10:58, Raghav Sharma <raghav.s@samsung.com> wrote: > > Add device tree clock binding definitions for CMU_PERIS > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> > Signed-off-by: Raghav Sharma <raghav.s@samsung.com> > --- Reviewed-by: Peter Griffin <peter.griffin@linaro.org> ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <CGME20261113104841epcas5p2823126ce22f44cc98fcbdf94403c32e3@epcas5p2.samsung.com>]
* [PATCH v3 04/14 RESEND] dt-bindings: clock: exynos8855: add hsi clock definitions [not found] ` <CGME20261113104841epcas5p2823126ce22f44cc98fcbdf94403c32e3@epcas5p2.samsung.com> @ 2026-11-13 11:06 ` Raghav Sharma 2026-11-13 11:02 ` Peter Griffin 0 siblings, 1 reply; 21+ messages in thread From: Raghav Sharma @ 2026-11-13 11:06 UTC (permalink / raw) To: krzk, s.nawrocki, cw00.choi, peter.griffin, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, raghav.s Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy, Krzysztof Kozlowski Add device tree clock binding definitions for CMU_HSI Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Raghav Sharma <raghav.s@samsung.com> --- .../clock/samsung,exynos8855-clock.yaml | 21 +++++++++++++++++++ .../dt-bindings/clock/samsung,exynos8855.h | 8 +++++++ 2 files changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml index 53fc8040e173..21928235d131 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml @@ -28,6 +28,7 @@ description: | properties: compatible: enum: + - samsung,exynos8855-cmu-hsi - samsung,exynos8855-cmu-peric - samsung,exynos8855-cmu-peris - samsung,exynos8855-cmu-top @@ -52,6 +53,26 @@ properties: Phandle to system registers interface. allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos8855-cmu-hsi + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_HSI NOC clock (from CMU_TOP) + - description: CMU_HSI UFS_EMBD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: ufs_embd + - if: properties: compatible: diff --git a/include/dt-bindings/clock/samsung,exynos8855.h b/include/dt-bindings/clock/samsung,exynos8855.h index 5d8b38a744b5..67cd97d8fab8 100644 --- a/include/dt-bindings/clock/samsung,exynos8855.h +++ b/include/dt-bindings/clock/samsung,exynos8855.h @@ -214,4 +214,12 @@ #define CLK_GOUT_WDT0_PERIS 8 #define CLK_GOUT_WDT1_PERIS 9 +/* CMU_HSI */ +#define CLK_MOUT_HSI_NOC_USER 1 +#define CLK_MOUT_HSI_UFS_EMBD_USER 2 +#define CLK_GOUT_CMU_HSI 3 +#define CLK_GOUT_SYSREG_HSI 4 +#define CLK_GOUT_UFS_EMBD_ACLK_HSI 5 +#define CLK_GOUT_UFS_EMBD_UNIPRO_HSI 6 + #endif /* _DT_BINDINGS_CLOCK_EXYNOS8855_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 04/14 RESEND] dt-bindings: clock: exynos8855: add hsi clock definitions 2026-11-13 11:06 ` [PATCH v3 04/14 RESEND] dt-bindings: clock: exynos8855: add hsi " Raghav Sharma @ 2026-11-13 11:02 ` Peter Griffin 0 siblings, 0 replies; 21+ messages in thread From: Peter Griffin @ 2026-11-13 11:02 UTC (permalink / raw) To: Raghav Sharma Cc: krzk, s.nawrocki, cw00.choi, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy, Krzysztof Kozlowski On Fri, 13 Nov 2026 at 10:58, Raghav Sharma <raghav.s@samsung.com> wrote: > > Add device tree clock binding definitions for CMU_HSI > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> > Signed-off-by: Raghav Sharma <raghav.s@samsung.com> > --- Reviewed-by: Peter Griffin <peter.griffin@linaro.org> > .../clock/samsung,exynos8855-clock.yaml | 21 +++++++++++++++++++ > .../dt-bindings/clock/samsung,exynos8855.h | 8 +++++++ > 2 files changed, 29 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml > index 53fc8040e173..21928235d131 100644 > --- a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml > +++ b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml > @@ -28,6 +28,7 @@ description: | > properties: > compatible: > enum: > + - samsung,exynos8855-cmu-hsi > - samsung,exynos8855-cmu-peric > - samsung,exynos8855-cmu-peris > - samsung,exynos8855-cmu-top > @@ -52,6 +53,26 @@ properties: > Phandle to system registers interface. > > allOf: > + - if: > + properties: > + compatible: > + contains: > + const: samsung,exynos8855-cmu-hsi > + > + then: > + properties: > + clocks: > + items: > + - description: External reference clock (76.8 MHz) > + - description: CMU_HSI NOC clock (from CMU_TOP) > + - description: CMU_HSI UFS_EMBD clock (from CMU_TOP) > + > + clock-names: > + items: > + - const: oscclk > + - const: bus > + - const: ufs_embd > + > - if: > properties: > compatible: > diff --git a/include/dt-bindings/clock/samsung,exynos8855.h b/include/dt-bindings/clock/samsung,exynos8855.h > index 5d8b38a744b5..67cd97d8fab8 100644 > --- a/include/dt-bindings/clock/samsung,exynos8855.h > +++ b/include/dt-bindings/clock/samsung,exynos8855.h > @@ -214,4 +214,12 @@ > #define CLK_GOUT_WDT0_PERIS 8 > #define CLK_GOUT_WDT1_PERIS 9 > > +/* CMU_HSI */ > +#define CLK_MOUT_HSI_NOC_USER 1 > +#define CLK_MOUT_HSI_UFS_EMBD_USER 2 > +#define CLK_GOUT_CMU_HSI 3 > +#define CLK_GOUT_SYSREG_HSI 4 > +#define CLK_GOUT_UFS_EMBD_ACLK_HSI 5 > +#define CLK_GOUT_UFS_EMBD_UNIPRO_HSI 6 > + > #endif /* _DT_BINDINGS_CLOCK_EXYNOS8855_H */ > -- > 2.34.1 > > ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <CGME20261113104844epcas5p4c1cb0c31de8b5b445f7f0060f81cf753@epcas5p4.samsung.com>]
* [PATCH v3 05/14 RESEND] dt-bindings: clock: exynos8855: add usb clock definitions [not found] ` <CGME20261113104844epcas5p4c1cb0c31de8b5b445f7f0060f81cf753@epcas5p4.samsung.com> @ 2026-11-13 11:06 ` Raghav Sharma 2026-11-13 11:03 ` Peter Griffin 0 siblings, 1 reply; 21+ messages in thread From: Raghav Sharma @ 2026-11-13 11:06 UTC (permalink / raw) To: krzk, s.nawrocki, cw00.choi, peter.griffin, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, raghav.s Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy, Krzysztof Kozlowski Add device tree clock binding definitions for CMU_USB Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Raghav Sharma <raghav.s@samsung.com> --- .../clock/samsung,exynos8855-clock.yaml | 21 +++++++++++++++++++ .../dt-bindings/clock/samsung,exynos8855.h | 8 +++++++ 2 files changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml index 21928235d131..c68a64eb35c5 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml @@ -32,6 +32,7 @@ properties: - samsung,exynos8855-cmu-peric - samsung,exynos8855-cmu-peris - samsung,exynos8855-cmu-top + - samsung,exynos8855-cmu-usb clocks: minItems: 1 @@ -143,6 +144,26 @@ allOf: required: - samsung,sysreg + - if: + properties: + compatible: + contains: + const: samsung,exynos8855-cmu-usb + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_USB NOC clock (from CMU_TOP) + - description: CMU_USB USB20DRD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: usb20drd + required: - compatible - "#clock-cells" diff --git a/include/dt-bindings/clock/samsung,exynos8855.h b/include/dt-bindings/clock/samsung,exynos8855.h index 67cd97d8fab8..f4261956ab4a 100644 --- a/include/dt-bindings/clock/samsung,exynos8855.h +++ b/include/dt-bindings/clock/samsung,exynos8855.h @@ -222,4 +222,12 @@ #define CLK_GOUT_UFS_EMBD_ACLK_HSI 5 #define CLK_GOUT_UFS_EMBD_UNIPRO_HSI 6 +/* CMU_USB */ +#define CLK_MOUT_USB_NOC_USER 1 +#define CLK_MOUT_USB_USB20DRD 2 +#define CLK_MOUT_USB_USB20DRD_USER 3 +#define CLK_DOUT_USB_NOC_DIV3 4 +#define CLK_GOUT_CMU_USB 5 +#define CLK_GOUT_SYSREG_USB 6 + #endif /* _DT_BINDINGS_CLOCK_EXYNOS8855_H */ -- 2.34.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 05/14 RESEND] dt-bindings: clock: exynos8855: add usb clock definitions 2026-11-13 11:06 ` [PATCH v3 05/14 RESEND] dt-bindings: clock: exynos8855: add usb " Raghav Sharma @ 2026-11-13 11:03 ` Peter Griffin 0 siblings, 0 replies; 21+ messages in thread From: Peter Griffin @ 2026-11-13 11:03 UTC (permalink / raw) To: Raghav Sharma Cc: krzk, s.nawrocki, cw00.choi, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy, Krzysztof Kozlowski On Fri, 13 Nov 2026 at 10:58, Raghav Sharma <raghav.s@samsung.com> wrote: > > Add device tree clock binding definitions for CMU_USB > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> > Signed-off-by: Raghav Sharma <raghav.s@samsung.com> > --- Reviewed-by: Peter Griffin <peter.griffin@linaro.org> > .../clock/samsung,exynos8855-clock.yaml | 21 +++++++++++++++++++ > .../dt-bindings/clock/samsung,exynos8855.h | 8 +++++++ > 2 files changed, 29 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml > index 21928235d131..c68a64eb35c5 100644 > --- a/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml > +++ b/Documentation/devicetree/bindings/clock/samsung,exynos8855-clock.yaml > @@ -32,6 +32,7 @@ properties: > - samsung,exynos8855-cmu-peric > - samsung,exynos8855-cmu-peris > - samsung,exynos8855-cmu-top > + - samsung,exynos8855-cmu-usb > > clocks: > minItems: 1 > @@ -143,6 +144,26 @@ allOf: > required: > - samsung,sysreg > > + - if: > + properties: > + compatible: > + contains: > + const: samsung,exynos8855-cmu-usb > + > + then: > + properties: > + clocks: > + items: > + - description: External reference clock (76.8 MHz) > + - description: CMU_USB NOC clock (from CMU_TOP) > + - description: CMU_USB USB20DRD clock (from CMU_TOP) > + > + clock-names: > + items: > + - const: oscclk > + - const: bus > + - const: usb20drd > + > required: > - compatible > - "#clock-cells" > diff --git a/include/dt-bindings/clock/samsung,exynos8855.h b/include/dt-bindings/clock/samsung,exynos8855.h > index 67cd97d8fab8..f4261956ab4a 100644 > --- a/include/dt-bindings/clock/samsung,exynos8855.h > +++ b/include/dt-bindings/clock/samsung,exynos8855.h > @@ -222,4 +222,12 @@ > #define CLK_GOUT_UFS_EMBD_ACLK_HSI 5 > #define CLK_GOUT_UFS_EMBD_UNIPRO_HSI 6 > > +/* CMU_USB */ > +#define CLK_MOUT_USB_NOC_USER 1 > +#define CLK_MOUT_USB_USB20DRD 2 > +#define CLK_MOUT_USB_USB20DRD_USER 3 > +#define CLK_DOUT_USB_NOC_DIV3 4 > +#define CLK_GOUT_CMU_USB 5 > +#define CLK_GOUT_SYSREG_USB 6 > + > #endif /* _DT_BINDINGS_CLOCK_EXYNOS8855_H */ > -- > 2.34.1 > > ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <CGME20261113104847epcas5p1d970255218f1ca78b19690bfd097f303@epcas5p1.samsung.com>]
* [PATCH v3 06/14 RESEND] clk: samsung: clk-pll: Add support for pll_4313 [not found] ` <CGME20261113104847epcas5p1d970255218f1ca78b19690bfd097f303@epcas5p1.samsung.com> @ 2026-11-13 11:06 ` Raghav Sharma 0 siblings, 0 replies; 21+ messages in thread From: Raghav Sharma @ 2026-11-13 11:06 UTC (permalink / raw) To: krzk, s.nawrocki, cw00.choi, peter.griffin, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, raghav.s Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy From: Alim Akhtar <alim.akhtar@samsung.com> PLLs 4313 are found in the Exynos8855 SoC and it is similar to pll_531x except for CON8 offset, so re-using code for pll_4313 Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Raghav Sharma <raghav.s@samsung.com> --- drivers/clk/samsung/clk-pll.c | 11 ++++++++++- drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 3d837bd74355..7b0756127306 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -1306,7 +1306,15 @@ static unsigned long samsung_pll531x_recalc_rate(struct clk_hw *hw, u64 mdiv, fout = parent_rate; pll_con0 = readl_relaxed(pll->con_reg); - pll_con8 = readl_relaxed(pll->con_reg + 20); + if (pll->type == pll_4313) { + /* Offset for PLL_CON8 which hold FDIV different for PLL_4313 + * which is PLL_LOCKTIME_OFFSET - 0x4 + */ + pll_con8 = readl_relaxed(pll->lock_reg - 4); + } else { + pll_con8 = readl_relaxed(pll->con_reg + 20); + } + mdiv = (pll_con0 >> PLL531X_MDIV_SHIFT) & PLL531X_MDIV_MASK; pdiv = (pll_con0 >> PLL531X_PDIV_SHIFT) & PLL531X_PDIV_MASK; sdiv = (pll_con0 >> PLL531X_SDIV_SHIFT) & PLL531X_SDIV_MASK; @@ -1729,6 +1737,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_309: case pll_531x: case pll_4311: + case pll_4313: init.ops = &samsung_pll531x_clk_ops; break; case pll_1031x: diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 2457cf47c109..4825e1f5b9db 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -49,6 +49,7 @@ enum samsung_pll_type { pll_0718x, pll_0732x, pll_4311, + pll_4313, pll_1017x, pll_1031x, pll_a9fracm, -- 2.34.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <CGME20261113104850epcas5p4ef9292af100475b1f12a2601bf5e1a84@epcas5p4.samsung.com>]
* [PATCH v3 07/14 RESEND] clk: samsung: exynos8855: add block top and peric clock support [not found] ` <CGME20261113104850epcas5p4ef9292af100475b1f12a2601bf5e1a84@epcas5p4.samsung.com> @ 2026-11-13 11:06 ` Raghav Sharma 2026-11-13 12:06 ` Peter Griffin 0 siblings, 1 reply; 21+ messages in thread From: Raghav Sharma @ 2026-11-13 11:06 UTC (permalink / raw) To: krzk, s.nawrocki, cw00.choi, peter.griffin, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, raghav.s Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy Register compatible and cmu_info data to support clocks. CMU_TOP & CMU_PERIC, these provide clocks for TOP & PERIC Co-developed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Raghav Sharma <raghav.s@samsung.com> --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos8855.c | 1130 ++++++++++++++++++++++++++ 2 files changed, 1131 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos8855.c diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index b3e994bd525d..99c2c304ff48 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos8895.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos990.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos8855.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o obj-$(CONFIG_EXYNOS_ACPM_CLK) += clk-acpm.o obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o diff --git a/drivers/clk/samsung/clk-exynos8855.c b/drivers/clk/samsung/clk-exynos8855.c new file mode 100644 index 000000000000..dcf58f2459b0 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos8855.c @@ -0,0 +1,1130 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 Samsung Electronics Co., Ltd. + * Author: Raghav Sharma <raghav.s@samsung.com> + * + * Common Clock Framework support for Exynos 8855 SoC. + */ + +#include <linux/clk-provider.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include <dt-bindings/clock/samsung,exynos8855.h> + +#include "clk.h" +#include "clk-exynos-arm64.h" + +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR_TOP (CLKCMU_DOUT_G3D_HTU + 1) +#define CLKS_NR_PERIC (CLK_GOUT_USI_PERIC + 1) + +#define EXYNOS8855_PERIC_GATE_DBG_OFFSET 0x2024 +#define EXYNOS8855_TOP_GATE_DBG_OFFSET 0x20A0 + +#define EXYNOS8855_DRCG_EN_OFFSET 0x104 +#define EXYNOS8855_MEMCLK_OFFSET 0x108 + +/* ---- CMU_TOP --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_TOP (0x13900000) */ +/* PLL */ +#define PLL_LOCKTIME_PLL_SHARED0 0x8 +#define PLL_LOCKTIME_PLL_SHARED1 0x10 +#define PLL_LOCKTIME_PLL_SHARED2 0x18 +#define PLL_LOCKTIME_PLL_MMC 0x20 +#define PLL_LOCKTIME_PLL_SHARED3 0x28 +#define PLL_LOCKTIME_PLL_SHARED4 0x38 +#define PLL_LOCKTIME_PLL_MIF_SWITCH 0x30 +#define PLL_CON0_PLL_MMC 0x1c0 +#define PLL_CON3_PLL_MMC 0x1cc +#define PLL_CON0_PLL_SHARED0 0x100 +#define PLL_CON3_PLL_SHARED0 0x10c +#define PLL_CON0_PLL_SHARED1 0x140 +#define PLL_CON3_PLL_SHARED1 0x14c +#define PLL_CON0_PLL_SHARED2 0x180 +#define PLL_CON3_PLL_SHARED2 0x18c +#define PLL_CON0_PLL_SHARED3 0x200 +#define PLL_CON3_PLL_SHARED3 0x20c +#define PLL_CON0_PLL_SHARED4 0x280 +#define PLL_CON3_PLL_SHARED4 0x28c +#define PLL_CON0_PLL_MIF_SWITCH 0x240 +#define PLL_CON3_PLL_MIF_SWITCH 0x24c + +/* MUX & DIV */ +#define CMU_TOP_CLK_CON_MUX_CLKCMU_AUD_CPU 0x1000 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_AUD_NOC 0x1004 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH 0x1008 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL0_NOCP 0x100c +#define CMU_TOP_CLK_CON_MUX_CLKCMU_DSU_SWITCH 0x1010 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH 0x1014 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK0 0x1018 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK1 0x101c +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK2 0x1020 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK3 0x1024 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK4 0x1028 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST_TOP 0x102c +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST 0x1030 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST_CPU 0x1034 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST_MIF0 0x1038 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CSIS_NOC 0x103c +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CSTAT_NOC 0x1040 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CSTAT_BYRP 0x1044 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_DPU_NOC 0x1048 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_G3DCORE_SWITCH 0x104c +#define CMU_TOP_CLK_CON_MUX_CLKCMU_M2M_NOC 0x1058 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_M2M_JPEG 0x105c +#define CMU_TOP_CLK_CON_MUX_CLKCMU_M2M_GDC 0x1060 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_MIF1_NOCP 0x1064 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_MFC_NOC 0x1068 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_MIF0_NOCP 0x106c +#define CMU_TOP_CLK_CON_MUX_CLKCMU_NOCL0_NOC 0x1070 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_NOCL1A_NOC 0x1074 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_NOC 0x1078 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_MMC_CARD 0x107c +#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_IP 0x1080 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_AUD_CPU 0x1800 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_AUD_NOC 0x1804 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1808 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL0_NOCP 0x180c +#define CMU_TOP_CLK_CON_DIV_CLKCMU_DSU_SWITCH 0x1810 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1814 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1818 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK1 0x181c +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1820 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK3 0x1824 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1828 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST_TOP 0x182c +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST 0x1830 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CSIS_NOC 0x1834 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU 0x1838 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF0 0x183c +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CSTAT_NOC 0x1840 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CSTAT_BYRP 0x1844 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_DPU_NOC 0x1848 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_G3DCORE_SWITCH 0x184c +#define CMU_TOP_CLK_CON_DIV_CLKCMU_M2M_NOC 0x1858 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_M2M_JPEG 0x185c +#define CMU_TOP_CLK_CON_DIV_CLKCMU_M2M_GDC 0x1860 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_MIF1_NOCP 0x1864 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_MFC_NOC 0x1868 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_MIF0_NOCP 0x186c +#define CMU_TOP_CLK_CON_DIV_CLKCMU_NOCL0_NOC 0x1870 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_NOCL1A_NOC 0x1874 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_NOC 0x1878 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_MMC_CARD 0x187c +#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_IP 0x1880 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_GIC 0x10c4 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_NOC 0x10c8 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_GIC 0x18c0 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_NOC 0x18c4 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_NOC 0x1050 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_UFS_EMBD 0x1054 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_NOC 0x1850 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD 0x1854 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_RGBP_NOC 0x1084 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_YUVP_NOC 0x1090 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_ALIVE_NOC 0x1094 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CSIS_DCPHY 0x1098 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CSIS_OIS 0x109c +#define CMU_TOP_CLK_CON_MUX_CLKCMU_ICPU_NOCD_0 0x10a0 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_ICPU_NOCD_1 0x10a4 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_GNPU0_NOC 0x10ac +#define CMU_TOP_CLK_CON_MUX_CLKCMU_GNPU0_XMAA 0x10b0 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_SDMA_NOC 0x10b4 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_DNC_HTU 0x10b8 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_DNC_NOC 0x10bc +#define CMU_TOP_CLK_CON_MUX_CLKCMU_PSP_NOC 0x10c0 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_G3D_NOCP 0x10cc +#define CMU_TOP_CLK_CON_MUX_CLKCMU_USI_NOC 0x10d0 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_USI_IP 0x10d4 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC 0x10d8 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_BOOST_RCO 0x10dc +#define CMU_TOP_CLK_CON_MUX_CLKCMU_MIF0_SWITCH 0x10e0 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_MIF1_SWITCH 0x10e4 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_NOCL1B_NOC 0x10e8 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH 0x10ec +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST_MIF1 0x10f0 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CSTAT_MCSC 0x10f4 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_G3D_HTU 0x10f8 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_RGBP_NOC 0x1884 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_YUVP_NOC 0x1890 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_ALIVE_NOC 0x1894 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CSIS_DCPHY 0x1898 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CSIS_OIS 0x189c +#define CMU_TOP_CLK_CON_DIV_CLKCMU_ICPU_NOCD_0 0x18a0 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_ICPU_NOCD_1 0x18a4 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_GNPU0_NOC 0x18a8 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_GNPU0_XMAA 0x18ac +#define CMU_TOP_CLK_CON_DIV_CLKCMU_SDMA_NOC 0x18b0 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_DNC_HTU 0x18b4 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_DNC_NOC 0x18b8 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_PSP_NOC 0x18bc +#define CMU_TOP_CLK_CON_DIV_CLKCMU_G3D_NOCP 0x18c8 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_USI_NOC 0x18cc +#define CMU_TOP_CLK_CON_DIV_CLKCMU_USI_IP 0x18d0 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL0_DBG_NOC 0x18d4 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_NOCL1B_NOC 0x18d8 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x18dc +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF1 0x18e0 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CSTAT_MCSC 0x18e4 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_G3D_HTU 0x18e8 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_USB_NOC 0x1088 +#define CMU_TOP_CLK_CON_MUX_CLKCMU_USB_USB20DRD 0x108c +#define CMU_TOP_CLK_CON_DIV_CLKCMU_USB_NOC 0x1888 +#define CMU_TOP_CLK_CON_DIV_CLKCMU_USB_USB20DRD 0x188c +#define CMU_TOP_CONTROLLER_OPTION0_CMU_CTRL 0x800 + +static const unsigned long top_clk_regs[] __initconst = { + PLL_LOCKTIME_PLL_MMC, + PLL_LOCKTIME_PLL_SHARED0, + PLL_LOCKTIME_PLL_SHARED1, + PLL_LOCKTIME_PLL_SHARED2, + PLL_LOCKTIME_PLL_SHARED3, + PLL_LOCKTIME_PLL_SHARED4, + PLL_LOCKTIME_PLL_MIF_SWITCH, + PLL_CON0_PLL_MMC, + PLL_CON3_PLL_MMC, + PLL_CON0_PLL_SHARED0, + PLL_CON3_PLL_SHARED0, + PLL_CON0_PLL_SHARED1, + PLL_CON3_PLL_SHARED1, + PLL_CON0_PLL_SHARED2, + PLL_CON3_PLL_SHARED2, + PLL_CON0_PLL_SHARED3, + PLL_CON3_PLL_SHARED3, + PLL_CON0_PLL_SHARED4, + PLL_CON3_PLL_SHARED4, + PLL_CON0_PLL_MIF_SWITCH, + PLL_CON3_PLL_MIF_SWITCH, + CMU_TOP_CLK_CON_MUX_CLKCMU_AUD_CPU, + CMU_TOP_CLK_CON_MUX_CLKCMU_AUD_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH, + CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL0_NOCP, + CMU_TOP_CLK_CON_MUX_CLKCMU_DSU_SWITCH, + CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH, + CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK0, + CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK1, + CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK2, + CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK3, + CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK4, + CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST_TOP, + CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST, + CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST_CPU, + CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST_MIF0, + CMU_TOP_CLK_CON_MUX_CLKCMU_CSIS_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_CSTAT_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_CSTAT_BYRP, + CMU_TOP_CLK_CON_MUX_CLKCMU_DPU_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_G3DCORE_SWITCH, + CMU_TOP_CLK_CON_MUX_CLKCMU_M2M_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_M2M_JPEG, + CMU_TOP_CLK_CON_MUX_CLKCMU_M2M_GDC, + CMU_TOP_CLK_CON_MUX_CLKCMU_MIF1_NOCP, + CMU_TOP_CLK_CON_MUX_CLKCMU_MFC_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_MIF0_NOCP, + CMU_TOP_CLK_CON_MUX_CLKCMU_NOCL0_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_NOCL1A_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_MMC_CARD, + CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_IP, + CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_MMC_CARD, + CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_IP, + CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_GIC, + CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_UFS_EMBD, + CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD, + CMU_TOP_CLK_CON_MUX_CLKCMU_RGBP_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_USB_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_USB_USB20DRD, + CMU_TOP_CLK_CON_MUX_CLKCMU_YUVP_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_ALIVE_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_CSIS_DCPHY, + CMU_TOP_CLK_CON_MUX_CLKCMU_CSIS_OIS, + CMU_TOP_CLK_CON_MUX_CLKCMU_ICPU_NOCD_0, + CMU_TOP_CLK_CON_MUX_CLKCMU_ICPU_NOCD_1, + CMU_TOP_CLK_CON_MUX_CLKCMU_GNPU0_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_GNPU0_XMAA, + CMU_TOP_CLK_CON_MUX_CLKCMU_SDMA_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_DNC_HTU, + CMU_TOP_CLK_CON_MUX_CLKCMU_DNC_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_PSP_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_GIC, + CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_G3D_NOCP, + CMU_TOP_CLK_CON_MUX_CLKCMU_USI_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_USI_IP, + CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_BOOST_RCO, + CMU_TOP_CLK_CON_MUX_CLKCMU_MIF0_SWITCH, + CMU_TOP_CLK_CON_MUX_CLKCMU_MIF1_SWITCH, + CMU_TOP_CLK_CON_MUX_CLKCMU_NOCL1B_NOC, + CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH, + CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST_MIF1, + CMU_TOP_CLK_CON_MUX_CLKCMU_CSTAT_MCSC, + CMU_TOP_CLK_CON_MUX_CLKCMU_G3D_HTU, + CMU_TOP_CLK_CON_DIV_CLKCMU_AUD_CPU, + CMU_TOP_CLK_CON_DIV_CLKCMU_AUD_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, + CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL0_NOCP, + CMU_TOP_CLK_CON_DIV_CLKCMU_DSU_SWITCH, + CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, + CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK0, + CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK1, + CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK2, + CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK3, + CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK4, + CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST_TOP, + CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST, + CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU, + CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF0, + CMU_TOP_CLK_CON_DIV_CLKCMU_CSIS_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_CSTAT_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_CSTAT_BYRP, + CMU_TOP_CLK_CON_DIV_CLKCMU_DPU_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_G3DCORE_SWITCH, + CMU_TOP_CLK_CON_DIV_CLKCMU_M2M_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_M2M_JPEG, + CMU_TOP_CLK_CON_DIV_CLKCMU_M2M_GDC, + CMU_TOP_CLK_CON_DIV_CLKCMU_MIF1_NOCP, + CMU_TOP_CLK_CON_DIV_CLKCMU_MFC_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_MIF0_NOCP, + CMU_TOP_CLK_CON_DIV_CLKCMU_NOCL0_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_NOCL1A_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_RGBP_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_USB_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_USB_USB20DRD, + CMU_TOP_CLK_CON_DIV_CLKCMU_YUVP_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_ALIVE_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_CSIS_DCPHY, + CMU_TOP_CLK_CON_DIV_CLKCMU_CSIS_OIS, + CMU_TOP_CLK_CON_DIV_CLKCMU_ICPU_NOCD_0, + CMU_TOP_CLK_CON_DIV_CLKCMU_ICPU_NOCD_1, + CMU_TOP_CLK_CON_DIV_CLKCMU_GNPU0_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_GNPU0_XMAA, + CMU_TOP_CLK_CON_DIV_CLKCMU_SDMA_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_DNC_HTU, + CMU_TOP_CLK_CON_DIV_CLKCMU_DNC_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_PSP_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_G3D_NOCP, + CMU_TOP_CLK_CON_DIV_CLKCMU_USI_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_USI_IP, + CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL0_DBG_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_NOCL1B_NOC, + CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, + CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF1, + CMU_TOP_CLK_CON_DIV_CLKCMU_CSTAT_MCSC, + CMU_TOP_CLK_CON_DIV_CLKCMU_G3D_HTU, + CMU_TOP_CONTROLLER_OPTION0_CMU_CTRL, +}; + +static const struct samsung_pll_clock top_pll_clks[] __initconst = { + PLL(pll_4313, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL), + PLL(pll_4313, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL), + PLL(pll_4313, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL), + PLL(pll_4313, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL), + PLL(pll_4313, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL), + PLL(pll_4313, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", + PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), + PLL(pll_4313, FOUT_MIF_SWITCH_PLL, "fout_mif_switch_pll", "oscclk", + PLL_LOCKTIME_PLL_MIF_SWITCH, PLL_CON3_PLL_MIF_SWITCH, NULL), +}; + +/* List of parent clocks for Muxes in CMU_TOP */ +PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" }; +PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" }; +PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" }; +PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" }; +PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" }; +PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" }; +PNAME(mout_mif_switch_pll_p) = { "oscclk", "fout_mif_switch_pll" }; + +/* New parent arrays for additional CMU_TOP MUX clocks */ +PNAME(mout_clkcmu_aud_cpu_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_aud_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared4_div3", "dout_shared3_div3"}; +PNAME(mout_clkcmu_cpucl0_switch_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared3_div1", + "dout_shared4_div3", "dout_shared3_div3"}; +PNAME(mout_clkcmu_cpucl0_nocp_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_dsu_switch_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared3_div1", + "dout_shared4_div3", "dout_shared3_div3"}; +PNAME(mout_clkcmu_cpucl1_switch_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared3_div1", + "dout_shared4_div3", "dout_shared3_div3"}; +PNAME(mout_clkcmu_cis_clk0_p) = { "oscclk", "dout_shared0_div4"}; +PNAME(mout_clkcmu_cis_clk1_p) = { "oscclk", "dout_shared0_div4"}; +PNAME(mout_clkcmu_cis_clk2_p) = { "oscclk", "dout_shared0_div4"}; +PNAME(mout_clkcmu_cis_clk3_p) = { "oscclk", "dout_shared0_div4"}; +PNAME(mout_clkcmu_cis_clk4_p) = { "oscclk", "dout_shared0_div4"}; +PNAME(mout_clkcmu_cmu_boost_top_p) = { "dout_shared0_div4", "dout_shared1_div4"}; +PNAME(mout_clkcmu_cmu_boost_p) = { "dout_shared0_div4", "dout_shared1_div4"}; +PNAME(mout_clkcmu_cmu_boost_cpu_p) = { "dout_shared0_div4", "dout_shared1_div4"}; +PNAME(mout_clkcmu_cmu_boost_mif0_p) = { "dout_shared0_div4", "dout_shared1_div4"}; +PNAME(mout_clkcmu_csis_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_cstat_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_cstat_byrp_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_dpu_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_g3dcore_switch_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_m2m_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_m2m_jpeg_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_m2m_gdc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_mif1_nocp_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_mfc_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_mif0_nocp_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_nocl0_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_nocl1a_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_rgbp_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_yuvp_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_alive_noc_p) = { "dout_shared0_div2", "dout_shared1_div4"}; +PNAME(mout_clkcmu_csis_dcphy_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared0_div4", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_csis_ois_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared0_div4", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_icpu_nocd_0_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div1", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_icpu_nocd_1_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div1", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_gnpu0_noc_p) = { "dout_shared2_div1", "dout_shared3_div1", + "dout_shared1_div2", "dout_shared1_div4", + "dout_shared4_div3", "dout_shared2_div1", + "dout_shared4_div3", "dout_shared3_div3"}; +PNAME(mout_clkcmu_gnpu0_xmaa_p) = { "dout_shared2_div1", "dout_shared3_div1", + "dout_shared1_div2", "dout_shared1_div4", + "dout_shared4_div3", "dout_shared2_div1", + "dout_shared4_div3", "dout_shared3_div3"}; +PNAME(mout_clkcmu_sdma_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared0_div3", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared4_div3", "dout_shared3_div3"}; +PNAME(mout_clkcmu_dnc_htu_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared0_div3", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared4_div3", "dout_shared3_div3"}; +PNAME(mout_clkcmu_dnc_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared0_div3", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared4_div3", "dout_shared3_div3"}; +PNAME(mout_clkcmu_psp_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared0_div3", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_g3d_nocp_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_usi_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "fout_mmc_pll_div2", + "dout_shared1_div4", "dout_shared3_div3"}; +PNAME(mout_clkcmu_usi_ip_p) = { "dout_shared0_div4", "dout_shared1_div4"}; +PNAME(mout_clkcmu_cpucl0_dbg_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_boost_rco_p) = { "oscclk", "clkalive_cmu_boost"}; +PNAME(mout_clkcmu_mif0_switch_p) = { "fout_mif_switch_pll_div1", "dout_shared0_div1", + "dout_shared0_div2", "dout_shared1_div1"}; +PNAME(mout_clkcmu_mif1_switch_p) = { "fout_mif_switch_pll_div1", "dout_shared0_div1", + "dout_shared0_div2", "dout_shared1_div1"}; +PNAME(mout_clkcmu_nocl1b_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_cpucl2_switch_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared3_div1", + "dout_shared4_div3", "dout_shared3_div3"}; +PNAME(mout_clkcmu_cmu_boost_mif1_p) = { "dout_shared0_div4", "dout_shared1_div4"}; +PNAME(mout_clkcmu_cstat_mcsc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_g3d_htu_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; + +PNAME(mout_clkcmu_peric_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "fout_mmc_pll_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_peric_mmc_card_p) = { "oscclk", "dout_shared0_div2", + "fout_mmc_pll_div1", "dout_shared1_div2", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_peric_ip_p) = { "dout_shared0_div4", "dout_shared1_div4"}; +PNAME(mout_clkcmu_peris_gic_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared1_div4", "dout_shared2_div2", + "fout_mmc_pll_clkout_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_peris_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared1_div4", "dout_shared2_div2", + "fout_mmc_pll_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_hsi_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_hsi_ufs_embd_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared1_div2", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_usb_noc_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared0_div4", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; +PNAME(mout_clkcmu_usb_usb20drd_p) = { "dout_shared0_div2", "dout_shared0_div3", + "dout_shared0_div4", "dout_shared1_div3", + "dout_shared2_div2", "dout_shared2_div3", + "dout_shared3_div2", "dout_shared3_div3"}; + +static const struct samsung_mux_clock top_mux_clks[] __initconst = { + MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, + PLL_CON0_PLL_SHARED0, 4, 1), + MUX(MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, + PLL_CON0_PLL_SHARED1, 4, 1), + MUX(MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p, + PLL_CON0_PLL_SHARED2, 4, 1), + MUX(MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p, + PLL_CON0_PLL_SHARED3, 4, 1), + MUX(MOUT_SHARED4_PLL, "mout_shared4_pll", mout_shared4_pll_p, + PLL_CON0_PLL_SHARED4, 4, 1), + MUX(MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, + PLL_CON0_PLL_MMC, 4, 1), + MUX(CLKCMU_MOUT_PERIC_NOC, "mout_clkcmu_peric_noc", + mout_clkcmu_peric_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_NOC, 0, 3), + MUX(CLKCMU_MOUT_PERIC_MMC_CARD, "mout_clkcmu_peric_mmc_card", + mout_clkcmu_peric_mmc_card_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_MMC_CARD, 0, 3), + MUX(CLKCMU_MOUT_PERIC_IP, "mout_clkcmu_peric_ip", + mout_clkcmu_peric_ip_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_IP, 0, 1), + MUX(CLKCMU_MOUT_PERIS_GIC, "mout_clkcmu_peris_gic", + mout_clkcmu_peris_gic_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_GIC, 0, 3), + MUX(CLKCMU_MOUT_PERIS_NOC, "mout_clkcmu_peris_noc", + mout_clkcmu_peris_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_NOC, 0, 3), + MUX(CLKCMU_MOUT_HSI_NOC, "mout_clkcmu_hsi_noc", + mout_clkcmu_hsi_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_NOC, 0, 3), + MUX(CLKCMU_MOUT_HSI_UFS_EMBD, "mout_clkcmu_hsi_ufs_embd", + mout_clkcmu_hsi_ufs_embd_p, CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_UFS_EMBD, 0, 3), + MUX(CLKCMU_MOUT_USB_NOC, "mout_clkcmu_usb_noc", + mout_clkcmu_usb_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_USB_NOC, 0, 3), + MUX(CLKCMU_MOUT_USB_USB20DRD, "mout_clkcmu_usb_usb20drd", + mout_clkcmu_usb_usb20drd_p, CMU_TOP_CLK_CON_MUX_CLKCMU_USB_USB20DRD, 0, 3), + MUX(MOUT_MIF_SWITCH_PLL, "mout_mif_switch_pll", mout_mif_switch_pll_p, + PLL_CON0_PLL_MIF_SWITCH, 4, 1), + MUX(CLKCMU_MOUT_AUD_CPU, "mout_clkcmu_aud_cpu", + mout_clkcmu_aud_cpu_p, CMU_TOP_CLK_CON_MUX_CLKCMU_AUD_CPU, 0, 3), + MUX(CLKCMU_MOUT_AUD_NOC, "mout_clkcmu_aud_noc", + mout_clkcmu_aud_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_AUD_NOC, 0, 3), + MUX(CLKCMU_MOUT_CPUCL0_SWITCH, "mout_clkcmu_cpucl0_switch", + mout_clkcmu_cpucl0_switch_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH, 0, 3), + MUX(CLKCMU_MOUT_CPUCL0_NOCP, "mout_clkcmu_cpucl0_nocp", + mout_clkcmu_cpucl0_nocp_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL0_NOCP, 0, 3), + MUX(CLKCMU_MOUT_DSU_SWITCH, "mout_clkcmu_dsu_switch", + mout_clkcmu_dsu_switch_p, CMU_TOP_CLK_CON_MUX_CLKCMU_DSU_SWITCH, 0, 3), + MUX(CLKCMU_MOUT_CPUCL1_SWITCH, "mout_clkcmu_cpucl1_switch", + mout_clkcmu_cpucl1_switch_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH, 0, 3), + MUX(CLKCMU_MOUT_CIS_CLK0, "mout_clkcmu_cis_clk0", + mout_clkcmu_cis_clk0_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK0, 0, 1), + MUX(CLKCMU_MOUT_CIS_CLK1, "mout_clkcmu_cis_clk1", + mout_clkcmu_cis_clk1_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK1, 0, 1), + MUX(CLKCMU_MOUT_CIS_CLK2, "mout_clkcmu_cis_clk2", + mout_clkcmu_cis_clk2_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK2, 0, 1), + MUX(CLKCMU_MOUT_CIS_CLK3, "mout_clkcmu_cis_clk3", + mout_clkcmu_cis_clk3_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK3, 0, 1), + MUX(CLKCMU_MOUT_CIS_CLK4, "mout_clkcmu_cis_clk4", + mout_clkcmu_cis_clk4_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK4, 0, 1), + MUX(CLKCMU_MOUT_CMU_BOOST_TOP, "mout_clkcmu_cmu_boost_top", + mout_clkcmu_cmu_boost_top_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST_TOP, 0, 1), + MUX(CLKCMU_MOUT_CMU_BOOST, "mout_clkcmu_cmu_boost", + mout_clkcmu_cmu_boost_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST, 0, 1), + MUX(CLKCMU_MOUT_CMU_BOOST_CPU, "mout_clkcmu_cmu_boost_cpu", + mout_clkcmu_cmu_boost_cpu_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST_CPU, 0, 1), + MUX(CLKCMU_MOUT_CMU_BOOST_MIF0, "mout_clkcmu_cmu_boost_mif0", + mout_clkcmu_cmu_boost_mif0_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST_MIF0, 0, 1), + MUX(CLKCMU_MOUT_CSIS_NOC, "mout_clkcmu_csis_noc", + mout_clkcmu_csis_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CSIS_NOC, 0, 3), + MUX(CLKCMU_MOUT_CSTAT_NOC, "mout_clkcmu_cstat_noc", + mout_clkcmu_cstat_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CSTAT_NOC, 0, 3), + MUX(CLKCMU_MOUT_CSTAT_BYRP, "mout_clkcmu_cstat_byrp", + mout_clkcmu_cstat_byrp_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CSTAT_BYRP, 0, 3), + MUX(CLKCMU_MOUT_DPU_NOC, "mout_clkcmu_dpu_noc", + mout_clkcmu_dpu_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_DPU_NOC, 0, 3), + MUX(CLKCMU_MOUT_G3DCORE_SWITCH, "mout_clkcmu_g3dcore_switch", + mout_clkcmu_g3dcore_switch_p, CMU_TOP_CLK_CON_MUX_CLKCMU_G3DCORE_SWITCH, 0, 3), + MUX(CLKCMU_MOUT_M2M_NOC, "mout_clkcmu_m2m_noc", + mout_clkcmu_m2m_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_M2M_NOC, 0, 3), + MUX(CLKCMU_MOUT_M2M_JPEG, "mout_clkcmu_m2m_jpeg", + mout_clkcmu_m2m_jpeg_p, CMU_TOP_CLK_CON_MUX_CLKCMU_M2M_JPEG, 0, 3), + MUX(CLKCMU_MOUT_M2M_GDC, "mout_clkcmu_m2m_gdc", + mout_clkcmu_m2m_gdc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_M2M_GDC, 0, 3), + MUX(CLKCMU_MOUT_MIF1_NOCP, "mout_clkcmu_mif1_nocp", + mout_clkcmu_mif1_nocp_p, CMU_TOP_CLK_CON_MUX_CLKCMU_MIF1_NOCP, 0, 3), + MUX(CLKCMU_MOUT_MFC_NOC, "mout_clkcmu_mfc_noc", + mout_clkcmu_mfc_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_MFC_NOC, 0, 3), + MUX(CLKCMU_MOUT_MIF0_NOCP, "mout_clkcmu_mif0_nocp", + mout_clkcmu_mif0_nocp_p, CMU_TOP_CLK_CON_MUX_CLKCMU_MIF0_NOCP, 0, 3), + MUX(CLKCMU_MOUT_NOCL0_NOC, "mout_clkcmu_nocl0_noc", + mout_clkcmu_nocl0_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_NOCL0_NOC, 0, 3), + MUX(CLKCMU_MOUT_NOCL1A_NOC, "mout_clkcmu_nocl1a_noc", + mout_clkcmu_nocl1a_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_NOCL1A_NOC, 0, 3), + MUX(CLKCMU_MOUT_RGBP_NOC, "mout_clkcmu_rgbp_noc", + mout_clkcmu_rgbp_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_RGBP_NOC, 0, 3), + MUX(CLKCMU_MOUT_YUVP_NOC, "mout_clkcmu_yuvp_noc", + mout_clkcmu_yuvp_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_YUVP_NOC, 0, 3), + MUX(CLKCMU_MOUT_ALIVE_NOC, "mout_clkcmu_alive_noc", + mout_clkcmu_alive_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_ALIVE_NOC, 0, 1), + MUX(CLKCMU_MOUT_CSIS_DCPHY, "mout_clkcmu_csis_dcphy", + mout_clkcmu_csis_dcphy_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CSIS_DCPHY, 0, 3), + MUX(CLKCMU_MOUT_CSIS_OIS, "mout_clkcmu_csis_ois", + mout_clkcmu_csis_ois_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CSIS_OIS, 0, 3), + MUX(CLKCMU_MOUT_ICPU_NOCD_0, "mout_clkcmu_icpu_nocd_0", + mout_clkcmu_icpu_nocd_0_p, CMU_TOP_CLK_CON_MUX_CLKCMU_ICPU_NOCD_0, 0, 3), + MUX(CLKCMU_MOUT_ICPU_NOCD_1, "mout_clkcmu_icpu_nocd_1", + mout_clkcmu_icpu_nocd_1_p, CMU_TOP_CLK_CON_MUX_CLKCMU_ICPU_NOCD_1, 0, 3), + MUX(CLKCMU_MOUT_GNPU0_NOC, "mout_clkcmu_gnpu0_noc", + mout_clkcmu_gnpu0_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_GNPU0_NOC, 0, 3), + MUX(CLKCMU_MOUT_GNPU0_XMAA, "mout_clkcmu_gnpu0_xmaa", + mout_clkcmu_gnpu0_xmaa_p, CMU_TOP_CLK_CON_MUX_CLKCMU_GNPU0_XMAA, 0, 3), + MUX(CLKCMU_MOUT_SDMA_NOC, "mout_clkcmu_sdma_noc", + mout_clkcmu_sdma_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_SDMA_NOC, 0, 3), + MUX(CLKCMU_MOUT_DNC_HTU, "mout_clkcmu_dnc_htu", + mout_clkcmu_dnc_htu_p, CMU_TOP_CLK_CON_MUX_CLKCMU_DNC_HTU, 0, 3), + MUX(CLKCMU_MOUT_DNC_NOC, "mout_clkcmu_dnc_noc", + mout_clkcmu_dnc_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_DNC_NOC, 0, 3), + MUX(CLKCMU_MOUT_PSP_NOC, "mout_clkcmu_psp_noc", + mout_clkcmu_psp_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_PSP_NOC, 0, 3), + MUX(CLKCMU_MOUT_G3D_NOCP, "mout_clkcmu_g3d_nocp", + mout_clkcmu_g3d_nocp_p, CMU_TOP_CLK_CON_MUX_CLKCMU_G3D_NOCP, 0, 3), + MUX(CLKCMU_MOUT_USI_NOC, "mout_clkcmu_usi_noc", + mout_clkcmu_usi_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_USI_NOC, 0, 3), + MUX(CLKCMU_MOUT_USI_IP, "mout_clkcmu_usi_ip", + mout_clkcmu_usi_ip_p, CMU_TOP_CLK_CON_MUX_CLKCMU_USI_IP, 0, 1), + MUX(CLKCMU_MOUT_CPUCL0_DBG_NOC, "mout_clkcmu_cpucl0_dbg_noc", + mout_clkcmu_cpucl0_dbg_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC, 0, 3), + MUX(CLKCMU_MOUT_BOOST_RCO, "mout_clkcmu_boost_rco", + mout_clkcmu_boost_rco_p, CMU_TOP_CLK_CON_MUX_CLKCMU_BOOST_RCO, 0, 1), + MUX(CLKCMU_MOUT_MIF0_SWITCH, "mout_clkcmu_mif0_switch", + mout_clkcmu_mif0_switch_p, CMU_TOP_CLK_CON_MUX_CLKCMU_MIF0_SWITCH, 0, 2), + MUX(CLKCMU_MOUT_MIF1_SWITCH, "mout_clkcmu_mif1_switch", + mout_clkcmu_mif1_switch_p, CMU_TOP_CLK_CON_MUX_CLKCMU_MIF1_SWITCH, 0, 2), + MUX(CLKCMU_MOUT_NOCL1B_NOC, "mout_clkcmu_nocl1b_noc", + mout_clkcmu_nocl1b_noc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_NOCL1B_NOC, 0, 3), + MUX(CLKCMU_MOUT_CPUCL2_SWITCH, "mout_clkcmu_cpucl2_switch", + mout_clkcmu_cpucl2_switch_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH, 0, 3), + MUX(CLKCMU_MOUT_CMU_BOOST_MIF1, "mout_clkcmu_cmu_boost_mif1", + mout_clkcmu_cmu_boost_mif1_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST_MIF1, 0, 1), + MUX(CLKCMU_MOUT_CSTAT_MCSC, "mout_clkcmu_cstat_mcsc", + mout_clkcmu_cstat_mcsc_p, CMU_TOP_CLK_CON_MUX_CLKCMU_CSTAT_MCSC, 0, 3), + MUX(CLKCMU_MOUT_G3D_HTU, "mout_clkcmu_g3d_htu", + mout_clkcmu_g3d_htu_p, CMU_TOP_CLK_CON_MUX_CLKCMU_G3D_HTU, 0, 3), +}; + +static const struct samsung_div_clock top_div_clks[] __initconst = { + DIV(CLKCMU_DOUT_PERIC_NOC, "dout_clkcmu_peric_noc", + "mout_clkcmu_peric_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_NOC, + 0, 4), + DIV(CLKCMU_DOUT_PERIC_MMC_CARD, "dout_clkcmu_peric_mmc_card", + "mout_clkcmu_peric_mmc_card", CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_MMC_CARD, + 0, 10), + DIV(CLKCMU_DOUT_PERIC_IP, "dout_clkcmu_peric_ip", + "mout_clkcmu_peric_ip", CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_IP, + 0, 4), + DIV(CLKCMU_DOUT_PERIS_GIC, "dout_clkcmu_peris_gic", + "mout_clkcmu_peris_gic", CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_GIC, + 0, 4), + DIV(CLKCMU_DOUT_PERIS_NOC, "dout_clkcmu_peris_noc", + "mout_clkcmu_peris_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_NOC, + 0, 4), + DIV(CLKCMU_DOUT_HSI_NOC, "dout_clkcmu_hsi_noc", + "mout_clkcmu_hsi_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_NOC, + 0, 4), + DIV(CLKCMU_DOUT_HSI_UFS_EMBD, "dout_clkcmu_hsi_ufs_embd", + "mout_clkcmu_hsi_ufs_embd", CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD, + 0, 4), + DIV(CLKCMU_DOUT_USB_NOC, "dout_clkcmu_usb_noc", + "mout_clkcmu_usb_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_USB_NOC, + 0, 4), + DIV(CLKCMU_DOUT_USB_USB20DRD, "dout_clkcmu_usb_usb20drd", + "mout_clkcmu_usb_usb20drd", CMU_TOP_CLK_CON_DIV_CLKCMU_USB_USB20DRD, + 0, 5), + DIV(CLKCMU_DOUT_AUD_CPU, "dout_clkcmu_aud_cpu", + "mout_clkcmu_aud_cpu", CMU_TOP_CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 4), + DIV(CLKCMU_DOUT_AUD_NOC, "dout_clkcmu_aud_noc", + "mout_clkcmu_aud_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_AUD_NOC, 0, 4), + DIV(CLKCMU_DOUT_CPUCL0_SWITCH, "dout_clkcmu_cpucl0_switch", + "mout_clkcmu_cpucl0_switch", CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 4), + DIV(CLKCMU_DOUT_CPUCL0_NOCP, "dout_clkcmu_cpucl0_nocp", + "mout_clkcmu_cpucl0_nocp", CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL0_NOCP, 0, 4), + DIV(CLKCMU_DOUT_DSU_SWITCH, "dout_clkcmu_dsu_switch", + "mout_clkcmu_dsu_switch", CMU_TOP_CLK_CON_DIV_CLKCMU_DSU_SWITCH, 0, 4), + DIV(CLKCMU_DOUT_CPUCL1_SWITCH, "dout_clkcmu_cpucl1_switch", + "mout_clkcmu_cpucl1_switch", CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 4), + DIV(CLKCMU_DOUT_CIS_CLK0, "dout_clkcmu_cis_clk0", + "mout_clkcmu_cis_clk0", CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5), + DIV(CLKCMU_DOUT_CIS_CLK1, "dout_clkcmu_cis_clk1", + "mout_clkcmu_cis_clk1", CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5), + DIV(CLKCMU_DOUT_CIS_CLK2, "dout_clkcmu_cis_clk2", + "mout_clkcmu_cis_clk2", CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5), + DIV(CLKCMU_DOUT_CIS_CLK3, "dout_clkcmu_cis_clk3", + "mout_clkcmu_cis_clk3", CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5), + DIV(CLKCMU_DOUT_CIS_CLK4, "dout_clkcmu_cis_clk4", + "mout_clkcmu_cis_clk4", CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5), + DIV(CLKCMU_DOUT_CMU_BOOST_TOP, "dout_clkcmu_cmu_boost_top", + "mout_clkcmu_cmu_boost_top", CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST_TOP, 0, 4), + DIV(CLKCMU_DOUT_CMU_BOOST, "dout_clkcmu_cmu_boost", + "mout_clkcmu_cmu_boost", CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST, 0, 4), + DIV(CLKCMU_DOUT_CMU_BOOST_CPU, "dout_clkcmu_cmu_boost_cpu", + "mout_clkcmu_cmu_boost_cpu", CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU, 0, 4), + DIV(CLKCMU_DOUT_CMU_BOOST_MIF0, "dout_clkcmu_cmu_boost_mif0", + "mout_clkcmu_cmu_boost_mif0", CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF0, 0, 4), + DIV(CLKCMU_DOUT_CSIS_NOC, "dout_clkcmu_csis_noc", + "mout_clkcmu_csis_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_CSIS_NOC, 0, 4), + DIV(CLKCMU_DOUT_CSTAT_NOC, "dout_clkcmu_cstat_noc", + "mout_clkcmu_cstat_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_CSTAT_NOC, 0, 4), + DIV(CLKCMU_DOUT_CSTAT_BYRP, "dout_clkcmu_cstat_byrp", + "mout_clkcmu_cstat_byrp", CMU_TOP_CLK_CON_DIV_CLKCMU_CSTAT_BYRP, 0, 4), + DIV(CLKCMU_DOUT_DPU_NOC, "dout_clkcmu_dpu_noc", + "mout_clkcmu_dpu_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_DPU_NOC, 0, 4), + DIV(CLKCMU_DOUT_G3DCORE_SWITCH, "dout_clkcmu_g3dcore_switch", + "mout_clkcmu_g3dcore_switch", CMU_TOP_CLK_CON_DIV_CLKCMU_G3DCORE_SWITCH, 0, 4), + DIV(CLKCMU_DOUT_M2M_NOC, "dout_clkcmu_m2m_noc", + "mout_clkcmu_m2m_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_M2M_NOC, 0, 4), + DIV(CLKCMU_DOUT_M2M_JPEG, "dout_clkcmu_m2m_jpeg", + "mout_clkcmu_m2m_jpeg", CMU_TOP_CLK_CON_DIV_CLKCMU_M2M_JPEG, 0, 4), + DIV(CLKCMU_DOUT_M2M_GDC, "dout_clkcmu_m2m_gdc", + "mout_clkcmu_m2m_gdc", CMU_TOP_CLK_CON_DIV_CLKCMU_M2M_GDC, 0, 4), + DIV(CLKCMU_DOUT_MIF1_NOCP, "dout_clkcmu_mif1_nocp", + "mout_clkcmu_mif1_nocp", CMU_TOP_CLK_CON_DIV_CLKCMU_MIF1_NOCP, 0, 4), + DIV(CLKCMU_DOUT_MFC_NOC, "dout_clkcmu_mfc_noc", + "mout_clkcmu_mfc_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_MFC_NOC, 0, 4), + DIV(CLKCMU_DOUT_MIF0_NOCP, "dout_clkcmu_mif0_nocp", + "mout_clkcmu_mif0_nocp", CMU_TOP_CLK_CON_DIV_CLKCMU_MIF0_NOCP, 0, 4), + DIV(CLKCMU_DOUT_NOCL0_NOC, "dout_clkcmu_nocl0_noc", + "mout_clkcmu_nocl0_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_NOCL0_NOC, 0, 4), + DIV(CLKCMU_DOUT_NOCL1A_NOC, "dout_clkcmu_nocl1a_noc", + "mout_clkcmu_nocl1a_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_NOCL1A_NOC, 0, 4), + DIV(CLKCMU_DOUT_RGBP_NOC, "dout_clkcmu_rgbp_noc", + "mout_clkcmu_rgbp_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_RGBP_NOC, 0, 4), + DIV(CLKCMU_DOUT_YUVP_NOC, "dout_clkcmu_yuvp_noc", + "mout_clkcmu_yuvp_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_YUVP_NOC, 0, 4), + DIV(CLKCMU_DOUT_ALIVE_NOC, "dout_clkcmu_alive_noc", + "mout_clkcmu_alive_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_ALIVE_NOC, 0, 4), + DIV(CLKCMU_DOUT_CSIS_DCPHY, "dout_clkcmu_csis_dcphy", + "mout_clkcmu_csis_dcphy", CMU_TOP_CLK_CON_DIV_CLKCMU_CSIS_DCPHY, 0, 4), + DIV(CLKCMU_DOUT_CSIS_OIS, "dout_clkcmu_csis_ois", + "mout_clkcmu_csis_ois", CMU_TOP_CLK_CON_DIV_CLKCMU_CSIS_OIS, 0, 4), + DIV(CLKCMU_DOUT_ICPU_NOCD_0, "dout_clkcmu_icpu_nocd_0", + "mout_clkcmu_icpu_nocd_0", CMU_TOP_CLK_CON_DIV_CLKCMU_ICPU_NOCD_0, 0, 4), + DIV(CLKCMU_DOUT_ICPU_NOCD_1, "dout_clkcmu_icpu_nocd_1", + "mout_clkcmu_icpu_nocd_1", CMU_TOP_CLK_CON_DIV_CLKCMU_ICPU_NOCD_1, 0, 4), + DIV(CLKCMU_DOUT_GNPU0_NOC, "dout_clkcmu_gnpu0_noc", + "mout_clkcmu_gnpu0_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_GNPU0_NOC, 0, 4), + DIV(CLKCMU_DOUT_GNPU0_XMAA, "dout_clkcmu_gnpu0_xmaa", + "mout_clkcmu_gnpu0_xmaa", CMU_TOP_CLK_CON_DIV_CLKCMU_GNPU0_XMAA, 0, 4), + DIV(CLKCMU_DOUT_SDMA_NOC, "dout_clkcmu_sdma_noc", + "mout_clkcmu_sdma_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_SDMA_NOC, 0, 4), + DIV(CLKCMU_DOUT_DNC_HTU, "dout_clkcmu_dnc_htu", + "mout_clkcmu_dnc_htu", CMU_TOP_CLK_CON_DIV_CLKCMU_DNC_HTU, 0, 4), + DIV(CLKCMU_DOUT_DNC_NOC, "dout_clkcmu_dnc_noc", + "mout_clkcmu_dnc_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_DNC_NOC, 0, 4), + DIV(CLKCMU_DOUT_PSP_NOC, "dout_clkcmu_psp_noc", + "mout_clkcmu_psp_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_PSP_NOC, 0, 4), + DIV(CLKCMU_DOUT_G3D_NOCP, "dout_clkcmu_g3d_nocp", + "mout_clkcmu_g3d_nocp", CMU_TOP_CLK_CON_DIV_CLKCMU_G3D_NOCP, 0, 4), + DIV(CLKCMU_DOUT_USI_NOC, "dout_clkcmu_usi_noc", + "mout_clkcmu_usi_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_USI_NOC, 0, 4), + DIV(CLKCMU_DOUT_USI_IP, "dout_clkcmu_usi_ip", + "mout_clkcmu_usi_ip", CMU_TOP_CLK_CON_DIV_CLKCMU_USI_IP, 0, 4), + DIV(CLKCMU_DOUT_CPUCL0_DBG_NOC, "dout_clkcmu_cpucl0_dbg_noc", + "mout_clkcmu_cpucl0_dbg_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL0_DBG_NOC, 0, 4), + DIV(CLKCMU_DOUT_NOCL1B_NOC, "dout_clkcmu_nocl1b_noc", + "mout_clkcmu_nocl1b_noc", CMU_TOP_CLK_CON_DIV_CLKCMU_NOCL1B_NOC, 0, 4), + DIV(CLKCMU_DOUT_CPUCL2_SWITCH, "dout_clkcmu_cpucl2_switch", + "mout_clkcmu_cpucl2_switch", CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 4), + DIV(CLKCMU_DOUT_CMU_BOOST_MIF1, "dout_clkcmu_cmu_boost_mif1", + "mout_clkcmu_cmu_boost_mif1", CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF1, 0, 4), + DIV(CLKCMU_DOUT_CSTAT_MCSC, "dout_clkcmu_cstat_mcsc", + "mout_clkcmu_cstat_mcsc", CMU_TOP_CLK_CON_DIV_CLKCMU_CSTAT_MCSC, 0, 4), + DIV(CLKCMU_DOUT_G3D_HTU, "dout_clkcmu_g3d_htu", + "mout_clkcmu_g3d_htu", CMU_TOP_CLK_CON_DIV_CLKCMU_G3D_HTU, 0, 4), +}; + +static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = { + FFACTOR(DOUT_SHARED0_DIV1, "dout_shared0_div1", + "mout_shared0_pll", 1, 1, 0), + FFACTOR(DOUT_SHARED0_DIV2, "dout_shared0_div2", + "mout_shared0_pll", 1, 2, 0), + FFACTOR(DOUT_SHARED0_DIV3, "dout_shared0_div3", + "mout_shared0_pll", 1, 3, 0), + FFACTOR(DOUT_SHARED0_DIV4, "dout_shared0_div4", + "mout_shared0_pll", 1, 4, 0), + FFACTOR(DOUT_SHARED1_DIV1, "dout_shared1_div1", + "mout_shared1_pll", 1, 1, 0), + FFACTOR(DOUT_SHARED1_DIV2, "dout_shared1_div2", + "mout_shared1_pll", 1, 2, 0), + FFACTOR(DOUT_SHARED1_DIV3, "dout_shared1_div3", + "mout_shared1_pll", 1, 3, 0), + FFACTOR(DOUT_SHARED1_DIV4, "dout_shared1_div4", + "mout_shared1_pll", 1, 4, 0), + FFACTOR(DOUT_SHARED2_DIV1, "dout_shared2_div1", + "mout_shared2_pll", 1, 1, 0), + FFACTOR(DOUT_SHARED2_DIV2, "dout_shared2_div2", + "mout_shared2_pll", 1, 2, 0), + FFACTOR(DOUT_SHARED2_DIV3, "dout_shared2_div3", + "mout_shared2_pll", 1, 3, 0), + FFACTOR(DOUT_SHARED2_DIV4, "dout_shared2_div4", + "mout_shared2_pll", 1, 4, 0), + FFACTOR(DOUT_SHARED3_DIV1, "dout_shared3_div1", + "mout_shared3_pll", 1, 1, 0), + FFACTOR(DOUT_SHARED3_DIV2, "dout_shared3_div2", + "mout_shared3_pll", 1, 2, 0), + FFACTOR(DOUT_SHARED3_DIV3, "dout_shared3_div3", + "mout_shared3_pll", 1, 3, 0), + FFACTOR(DOUT_SHARED3_DIV4, "dout_shared3_div4", + "mout_shared3_pll", 1, 4, 0), + FFACTOR(DOUT_SHARED4_DIV1, "dout_shared4_div1", + "mout_shared4_pll", 1, 1, 0), + FFACTOR(DOUT_SHARED4_DIV2, "dout_shared4_div2", + "mout_shared4_pll", 1, 2, 0), + FFACTOR(DOUT_SHARED4_DIV3, "dout_shared4_div3", + "mout_shared4_pll", 1, 3, 0), + FFACTOR(DOUT_SHARED4_DIV4, "dout_shared4_div4", + "mout_shared4_pll", 1, 4, 0), + FFACTOR(FOUT_MMC_PLL_DIV1, "fout_mmc_pll_div1", + "mout_mmc_pll", 1, 1, 0), + FFACTOR(FOUT_MMC_PLL_DIV2, "fout_mmc_pll_div2", + "mout_mmc_pll", 1, 2, 0), + FFACTOR(FOUT_MMC_PLL_CLKOUT_DIV2, "fout_mmc_pll_clkout_div2", + "mout_mmc_pll", 1, 2, 0), + FFACTOR(FOUT_MMC_PLL_DIV3, "fout_mmc_pll_div3", + "mout_mmc_pll", 1, 3, 0), + FFACTOR(FOUT_MMC_PLL_DIV4, "fout_mmc_pll_div4", + "mout_mmc_pll", 1, 4, 0), + FFACTOR(FOUT_MIF_SWITCH_PLL_DIV1, "fout_mif_switch_pll_div1", + "mout_mif_switch_pll", 1, 1, 0), + FFACTOR(FOUT_MIF_SWITCH_PLL_DIV2, "fout_mif_switch_pll_div2", + "mout_mif_switch_pll", 1, 2, 0), + FFACTOR(FOUT_MIF_SWITCH_PLL_DIV3, "fout_mif_switch_pll_div3", + "mout_mif_switch_pll", 1, 3, 0), + FFACTOR(FOUT_MIF_SWITCH_PLL_DIV4, "fout_mif_switch_pll_div4", + "mout_mif_switch_pll", 1, 4, 0), +}; + +static const struct samsung_fixed_rate_clock top_fixed_rate_clks[] __initconst = { + FRATE(0, "oscclk_usb_link", NULL, 0, 19200000), +}; + +static const struct samsung_cmu_info top_cmu_info __initconst = { + .pll_clks = top_pll_clks, + .nr_pll_clks = ARRAY_SIZE(top_pll_clks), + .mux_clks = top_mux_clks, + .nr_mux_clks = ARRAY_SIZE(top_mux_clks), + .div_clks = top_div_clks, + .nr_div_clks = ARRAY_SIZE(top_div_clks), + .fixed_factor_clks = top_fixed_factor_clks, + .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), + .fixed_clks = top_fixed_rate_clks, + .nr_fixed_clks = ARRAY_SIZE(top_fixed_rate_clks), + .nr_clk_ids = CLKS_NR_TOP, + .clk_regs = top_clk_regs, + .nr_clk_regs = ARRAY_SIZE(top_clk_regs), + .auto_clock_gate = true, + .gate_dbg_offset = EXYNOS8855_TOP_GATE_DBG_OFFSET, + .option_offset = CMU_TOP_CONTROLLER_OPTION0_CMU_CTRL, +}; + +static void __init exynos8855_cmu_top_init(struct device_node *np) +{ + exynos_arm64_register_cmu(NULL, np, &top_cmu_info); +} + +/* Register CMU_TOP early, as it's a dependency for other early domains */ +CLK_OF_DECLARE(exynos8855_cmu_top, "samsung,exynos8855-cmu-top", + exynos8855_cmu_top_init); + +/* ---- CMU_PERIC --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIC (0x15400000) */ +#define CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_IP_USER 0x600 +#define CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_MMC_CARD_USER 0x610 +#define CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_NOC_USER 0x620 +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_I2C 0x1000 +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_UART_DBG 0x1004 +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI00 0x1008 +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI01 0x100c +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI02 0x1010 +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI03 0x1014 +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI04 0x1018 +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI09_USI_OIS 0x101c +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI10_USI_OIS 0x1020 +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_NOCP 0x1800 +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_UART_DBG 0x1804 +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI00_USI 0x1808 +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI01_USI 0x180c +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI02_USI 0x1810 +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI03_USI 0x1814 +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI04_USI 0x1818 +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI09_USI_OIS 0x181c +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI10_USI_OIS 0x1820 +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI_I2C 0x1824 +#define CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_CMU_PERIC_IPCLKPORT_PCLK 0x2004 +#define CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_SYSREG_PERIC_IPCLKPORT_PCLK 0x2060 +#define CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_UART_DBG_IPCLKPORT_PCLK 0x2064 +#define CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_USI00_USI_IPCLKPORT_PCLK 0x206c +#define CMU_PERIC_CONTROLLER_OPTION0_CMU_CTRL 0x800 + +static const unsigned long peric_clk_regs[] __initconst = { + CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_IP_USER, + CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_MMC_CARD_USER, + CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_NOC_USER, + CMU_PERIC_CLK_CON_MUX_CLK_PERIC_I2C, + CMU_PERIC_CLK_CON_MUX_CLK_PERIC_UART_DBG, + CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI00, + CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI01, + CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI02, + CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI03, + CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI04, + CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI09_USI_OIS, + CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI10_USI_OIS, + CMU_PERIC_CLK_CON_DIV_CLK_PERIC_NOCP, + CMU_PERIC_CLK_CON_DIV_CLK_PERIC_UART_DBG, + CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI00_USI, + CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI01_USI, + CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI02_USI, + CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI03_USI, + CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI04_USI, + CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI09_USI_OIS, + CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI10_USI_OIS, + CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI_I2C, + CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_CMU_PERIC_IPCLKPORT_PCLK, + CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_SYSREG_PERIC_IPCLKPORT_PCLK, + CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_UART_DBG_IPCLKPORT_PCLK, + CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_USI00_USI_IPCLKPORT_PCLK, + CMU_PERIC_CONTROLLER_OPTION0_CMU_CTRL, +}; + +/* List of parent clocks for Muxes in CMU_PERIC */ +PNAME(mout_clkcmu_peric_ip_user_p) = { "oscclk", "dout_clkcmu_peric_ip" }; +PNAME(mout_clkcmu_peric_mmc_card_user_p) = { "oscclk", "dout_clkcmu_peric_mmc_card" }; +PNAME(mout_clkcmu_peric_noc_user_p) = { "oscclk", "dout_clkcmu_peric_noc" }; +PNAME(mout_clkcmu_peric_i2c_p) = { "oscclk", "mout_clkcmu_peric_ip_user" }; +PNAME(mout_clkcmu_peric_uart_dbg_p) = { "oscclk", "mout_clkcmu_peric_ip_user" }; +PNAME(mout_clkcmu_peric_usi0n_p) = { "oscclk", "mout_clkcmu_peric_ip_user" }; +PNAME(mout_clkcmu_peric_usi09_usi_ois_p) = { "oscclk", "mout_clkcmu_peric_ip_user" }; +PNAME(mout_clkcmu_peric_usi10_usi_ois_p) = { "oscclk", "mout_clkcmu_peric_ip_user" }; + +static const struct samsung_mux_clock peric_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIC_IP_USER, "mout_clkcmu_peric_ip_user", + mout_clkcmu_peric_ip_user_p, CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_IP_USER, 4, 1), + MUX(CLK_MOUT_PERIC_MMC_CARD_USER, "mout_clkcmu_peric_mmc_card_user", + mout_clkcmu_peric_mmc_card_user_p, CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_MMC_CARD_USER, + 4, 1), + MUX(CLK_MOUT_PERIC_NOC_USER, "mout_clkcmu_peric_noc_user", + mout_clkcmu_peric_noc_user_p, CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_NOC_USER, 4, 1), + MUX(CLK_MOUT_PERIC_I2C, "mout_clkcmu_peric_i2c", + mout_clkcmu_peric_i2c_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_I2C, 0, 1), + MUX(CLK_MOUT_PERIC_UART_DBG, "mout_clkcmu_peric_uart_dbg", + mout_clkcmu_peric_uart_dbg_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_UART_DBG, 0, 1), + MUX(CLK_MOUT_PERIC_USI00, "mout_clkcmu_peric_usi00", + mout_clkcmu_peric_usi0n_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI00, 0, 1), + MUX(CLK_MOUT_PERIC_USI01, "mout_clkcmu_peric_usi01", + mout_clkcmu_peric_usi0n_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI01, 0, 1), + MUX(CLK_MOUT_PERIC_USI02, "mout_clkcmu_peric_usi02", + mout_clkcmu_peric_usi0n_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI02, 0, 1), + MUX(CLK_MOUT_PERIC_USI03, "mout_clkcmu_peric_usi03", + mout_clkcmu_peric_usi0n_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI03, 0, 1), + MUX(CLK_MOUT_PERIC_USI04, "mout_clkcmu_peric_usi04", + mout_clkcmu_peric_usi0n_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI04, 0, 1), + MUX(CLK_MOUT_PERIC_USI09_USI_OIS, "mout_clkcmu_peric_usi09_usi_ois", + mout_clkcmu_peric_usi09_usi_ois_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI09_USI_OIS, 0, 1), + MUX(CLK_MOUT_PERIC_USI10_USI_OIS, "mout_clkcmu_peric_usi10_usi_ois", + mout_clkcmu_peric_usi10_usi_ois_p, CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI10_USI_OIS, 0, 1), +}; + +static const struct samsung_div_clock peric_div_clks[] __initconst = { + DIV(CLK_DOUT_PERIC_NOCP, "dout_clkcmu_peric_nocp", + "mout_clkcmu_peric_noc_user", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_NOCP, + 0, 4), + DIV(CLK_DOUT_PERIC_UART_DBG, "dout_clkcmu_peric_uart_dbg", + "mout_clkcmu_peric_uart_dbg", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_UART_DBG, + 0, 4), + DIV(CLK_DOUT_PERIC_USI00_USI, "dout_clkcmu_peric_usi00_usi", + "mout_clkcmu_peric_usi00", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI00_USI, + 0, 4), + DIV(CLK_DOUT_PERIC_USI01_USI, "dout_clkcmu_peric_usi01_usi", + "mout_clkcmu_peric_usi01", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI01_USI, + 0, 4), + DIV(CLK_DOUT_PERIC_USI02_USI, "dout_clkcmu_peric_usi02_usi", + "mout_clkcmu_peric_usi02", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI02_USI, + 0, 4), + DIV(CLK_DOUT_PERIC_USI03_USI, "dout_clkcmu_peric_usi03_usi", + "mout_clkcmu_peric_usi03", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI03_USI, + 0, 4), + DIV(CLK_DOUT_PERIC_USI04_USI, "dout_clkcmu_peric_usi04_usi", + "mout_clkcmu_peric_usi04", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI04_USI, + 0, 4), + DIV(CLK_DOUT_PERIC_USI09_USI_OIS, "dout_clkcmu_peric_usi09_usi_ois", + "mout_clkcmu_peric_usi09_usi_ois", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI09_USI_OIS, + 0, 4), + DIV(CLK_DOUT_PERIC_USI10_USI_OIS, "dout_clkcmu_peric_usi10_usi_ois", + "mout_clkcmu_peric_usi10_usi_ois", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI10_USI_OIS, + 0, 4), + DIV(CLK_DOUT_PERIC_USI_I2C, "dout_clkcmu_peric_usi_i2c", + "mout_clkcmu_peric_i2c", CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI_I2C, + 0, 4), +}; + +static const struct samsung_gate_clock peric_gate_clks[] __initconst = { + GATE(CLK_GOUT_CMU_PERIC, "gout_cmu_peric", + "dout_clkcmu_peric_nocp", + CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_CMU_PERIC_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_SYSREG_PERIC, "gout_sysreg_peric", + "dout_clkcmu_peric_nocp", + CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_SYSREG_PERIC_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_UART_DBG_PERIC, "gout_uart_dbg_peric", + "dout_clkcmu_peric_uart_dbg", + CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_UART_DBG_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_USI_PERIC, "gout_usi_peric", + "dout_clkcmu_peric_nocp", + CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_USI00_USI_IPCLKPORT_PCLK, + 21, 0, 0), +}; + +static const unsigned long dcrg_memclk_sysreg[] __initconst = { + EXYNOS8855_DRCG_EN_OFFSET, + EXYNOS8855_MEMCLK_OFFSET, +}; + +static const struct samsung_cmu_info peric_cmu_info __initconst = { + .mux_clks = peric_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peric_mux_clks), + .div_clks = peric_div_clks, + .nr_div_clks = ARRAY_SIZE(peric_div_clks), + .gate_clks = peric_gate_clks, + .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), + .nr_clk_ids = CLKS_NR_PERIC, + .clk_regs = peric_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), + .sysreg_clk_regs = dcrg_memclk_sysreg, + .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg), + .clk_name = "bus", + .auto_clock_gate = true, + .gate_dbg_offset = EXYNOS8855_PERIC_GATE_DBG_OFFSET, + .option_offset = CMU_PERIC_CONTROLLER_OPTION0_CMU_CTRL, + .drcg_offset = EXYNOS8855_DRCG_EN_OFFSET, + .memclk_offset = EXYNOS8855_MEMCLK_OFFSET, +}; + +static int __init exynos8855_cmu_probe(struct platform_device *pdev) +{ + const struct samsung_cmu_info *info; + struct device *dev = &pdev->dev; + + info = of_device_get_match_data(dev); + exynos_arm64_register_cmu(dev, dev->of_node, info); + + return 0; +} + +static const struct of_device_id exynos8855_cmu_of_match[] = { + { + .compatible = "samsung,exynos8855-cmu-peric", + .data = &peric_cmu_info, + }, { + .compatible = "samsung,exynos8855-cmu-top", + .data = &top_cmu_info, + }, + { } +}; + +static struct platform_driver exynos8855_cmu_driver __refdata = { + .driver = { + .name = "exynos8855-cmu", + .of_match_table = exynos8855_cmu_of_match, + .suppress_bind_attrs = true, + }, + .probe = exynos8855_cmu_probe, +}; + +static int __init exynos8855_cmu_init(void) +{ + return platform_driver_register(&exynos8855_cmu_driver); +} +core_initcall(exynos8855_cmu_init); -- 2.34.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v3 07/14 RESEND] clk: samsung: exynos8855: add block top and peric clock support 2026-11-13 11:06 ` [PATCH v3 07/14 RESEND] clk: samsung: exynos8855: add block top and peric clock support Raghav Sharma @ 2026-11-13 12:06 ` Peter Griffin 0 siblings, 0 replies; 21+ messages in thread From: Peter Griffin @ 2026-11-13 12:06 UTC (permalink / raw) To: Raghav Sharma Cc: krzk, s.nawrocki, cw00.choi, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy Hi Raghav, Nice to see you got the auto clock mode working on this SoC. Great Work! See some inline comments below On Fri, 13 Nov 2026 at 10:53, Raghav Sharma <raghav.s@samsung.com> wrote: > > Register compatible and cmu_info data to support clocks. > CMU_TOP & CMU_PERIC, these provide clocks for TOP & PERIC > > Co-developed-by: Alim Akhtar <alim.akhtar@samsung.com> > Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> > Signed-off-by: Raghav Sharma <raghav.s@samsung.com> > --- > drivers/clk/samsung/Makefile | 1 + > drivers/clk/samsung/clk-exynos8855.c | 1130 ++++++++++++++++++++++++++ > 2 files changed, 1131 insertions(+) > create mode 100644 drivers/clk/samsung/clk-exynos8855.c > > diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile > index b3e994bd525d..99c2c304ff48 100644 > --- a/drivers/clk/samsung/Makefile > +++ b/drivers/clk/samsung/Makefile > @@ -29,6 +29,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos8895.o > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos990.o > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o > +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos8855.o > obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o > obj-$(CONFIG_EXYNOS_ACPM_CLK) += clk-acpm.o > obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o > diff --git a/drivers/clk/samsung/clk-exynos8855.c b/drivers/clk/samsung/clk-exynos8855.c > new file mode 100644 > index 000000000000..dcf58f2459b0 > --- /dev/null > +++ b/drivers/clk/samsung/clk-exynos8855.c > @@ -0,0 +1,1130 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2026 Samsung Electronics Co., Ltd. > + * Author: Raghav Sharma <raghav.s@samsung.com> > + * > + * Common Clock Framework support for Exynos 8855 SoC. > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/of.h> > +#include <linux/platform_device.h> > + > +#include <dt-bindings/clock/samsung,exynos8855.h> > + > +#include "clk.h" > +#include "clk-exynos-arm64.h" > + > +/* NOTE: Must be equal to the last clock ID increased by one */ > +#define CLKS_NR_TOP (CLKCMU_DOUT_G3D_HTU + 1) > +#define CLKS_NR_PERIC (CLK_GOUT_USI_PERIC + 1) > + > +#define EXYNOS8855_PERIC_GATE_DBG_OFFSET 0x2024 > +#define EXYNOS8855_TOP_GATE_DBG_OFFSET 0x20A0 > + > +#define EXYNOS8855_DRCG_EN_OFFSET 0x104 > +#define EXYNOS8855_MEMCLK_OFFSET 0x108 > + > +/* ---- CMU_TOP --------------------------------------------------------- */ > + > +/* Register Offset definitions for CMU_TOP (0x13900000) */ > +/* PLL */ IIUC in clk-pll.c you are using PLL_LOCKTIME_PLL_SHARED* - 4 for the PLL_CON8 register offset? I was expecting to see those registers defined here > +#define PLL_LOCKTIME_PLL_SHARED0 0x8 > +#define PLL_LOCKTIME_PLL_SHARED1 0x10 > +#define PLL_LOCKTIME_PLL_SHARED2 0x18 > +#define PLL_LOCKTIME_PLL_MMC 0x20 > +#define PLL_LOCKTIME_PLL_SHARED3 0x28 > +#define PLL_LOCKTIME_PLL_SHARED4 0x38 > +#define PLL_LOCKTIME_PLL_MIF_SWITCH 0x30 > +#define PLL_CON0_PLL_MMC 0x1c0 > +#define PLL_CON3_PLL_MMC 0x1cc > +#define PLL_CON0_PLL_SHARED0 0x100 > +#define PLL_CON3_PLL_SHARED0 0x10c > +#define PLL_CON0_PLL_SHARED1 0x140 > +#define PLL_CON3_PLL_SHARED1 0x14c > +#define PLL_CON0_PLL_SHARED2 0x180 > +#define PLL_CON3_PLL_SHARED2 0x18c > +#define PLL_CON0_PLL_SHARED3 0x200 > +#define PLL_CON3_PLL_SHARED3 0x20c > +#define PLL_CON0_PLL_SHARED4 0x280 > +#define PLL_CON3_PLL_SHARED4 0x28c > +#define PLL_CON0_PLL_MIF_SWITCH 0x240 > +#define PLL_CON3_PLL_MIF_SWITCH 0x24c > + > +/* MUX & DIV */ > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_AUD_CPU 0x1000 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_AUD_NOC 0x1004 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH 0x1008 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL0_NOCP 0x100c > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_DSU_SWITCH 0x1010 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH 0x1014 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK0 0x1018 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK1 0x101c > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK2 0x1020 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK3 0x1024 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CIS_CLK4 0x1028 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST_TOP 0x102c > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST 0x1030 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST_CPU 0x1034 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST_MIF0 0x1038 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CSIS_NOC 0x103c > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CSTAT_NOC 0x1040 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CSTAT_BYRP 0x1044 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_DPU_NOC 0x1048 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_G3DCORE_SWITCH 0x104c > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_M2M_NOC 0x1058 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_M2M_JPEG 0x105c > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_M2M_GDC 0x1060 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_MIF1_NOCP 0x1064 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_MFC_NOC 0x1068 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_MIF0_NOCP 0x106c > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_NOCL0_NOC 0x1070 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_NOCL1A_NOC 0x1074 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_NOC 0x1078 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_MMC_CARD 0x107c > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIC_IP 0x1080 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_AUD_CPU 0x1800 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_AUD_NOC 0x1804 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1808 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL0_NOCP 0x180c > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_DSU_SWITCH 0x1810 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1814 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1818 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK1 0x181c > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1820 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK3 0x1824 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1828 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST_TOP 0x182c > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST 0x1830 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CSIS_NOC 0x1834 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU 0x1838 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF0 0x183c > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CSTAT_NOC 0x1840 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CSTAT_BYRP 0x1844 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_DPU_NOC 0x1848 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_G3DCORE_SWITCH 0x184c > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_M2M_NOC 0x1858 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_M2M_JPEG 0x185c > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_M2M_GDC 0x1860 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_MIF1_NOCP 0x1864 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_MFC_NOC 0x1868 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_MIF0_NOCP 0x186c > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_NOCL0_NOC 0x1870 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_NOCL1A_NOC 0x1874 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_NOC 0x1878 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_MMC_CARD 0x187c > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIC_IP 0x1880 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_GIC 0x10c4 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_PERIS_NOC 0x10c8 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_GIC 0x18c0 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_PERIS_NOC 0x18c4 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_NOC 0x1050 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_HSI_UFS_EMBD 0x1054 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_NOC 0x1850 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD 0x1854 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_RGBP_NOC 0x1084 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_YUVP_NOC 0x1090 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_ALIVE_NOC 0x1094 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CSIS_DCPHY 0x1098 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CSIS_OIS 0x109c > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_ICPU_NOCD_0 0x10a0 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_ICPU_NOCD_1 0x10a4 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_GNPU0_NOC 0x10ac > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_GNPU0_XMAA 0x10b0 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_SDMA_NOC 0x10b4 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_DNC_HTU 0x10b8 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_DNC_NOC 0x10bc > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_PSP_NOC 0x10c0 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_G3D_NOCP 0x10cc > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_USI_NOC 0x10d0 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_USI_IP 0x10d4 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC 0x10d8 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_BOOST_RCO 0x10dc > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_MIF0_SWITCH 0x10e0 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_MIF1_SWITCH 0x10e4 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_NOCL1B_NOC 0x10e8 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH 0x10ec > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CMU_BOOST_MIF1 0x10f0 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_CSTAT_MCSC 0x10f4 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_G3D_HTU 0x10f8 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_RGBP_NOC 0x1884 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_YUVP_NOC 0x1890 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_ALIVE_NOC 0x1894 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CSIS_DCPHY 0x1898 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CSIS_OIS 0x189c > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_ICPU_NOCD_0 0x18a0 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_ICPU_NOCD_1 0x18a4 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_GNPU0_NOC 0x18a8 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_GNPU0_XMAA 0x18ac > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_SDMA_NOC 0x18b0 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_DNC_HTU 0x18b4 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_DNC_NOC 0x18b8 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_PSP_NOC 0x18bc > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_G3D_NOCP 0x18c8 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_USI_NOC 0x18cc > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_USI_IP 0x18d0 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL0_DBG_NOC 0x18d4 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_NOCL1B_NOC 0x18d8 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x18dc > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF1 0x18e0 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_CSTAT_MCSC 0x18e4 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_G3D_HTU 0x18e8 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_USB_NOC 0x1088 > +#define CMU_TOP_CLK_CON_MUX_CLKCMU_USB_USB20DRD 0x108c > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_USB_NOC 0x1888 > +#define CMU_TOP_CLK_CON_DIV_CLKCMU_USB_USB20DRD 0x188c > +#define CMU_TOP_CONTROLLER_OPTION0_CMU_CTRL 0x800 > + > +static const unsigned long top_clk_regs[] __initconst = { > + PLL_LOCKTIME_PLL_MMC, and also here > + PLL_LOCKTIME_PLL_SHARED0, > + PLL_LOCKTIME_PLL_SHARED1, > + PLL_LOCKTIME_PLL_SHARED2, [..] > +/* Register CMU_TOP early, as it's a dependency for other early domains */ > +CLK_OF_DECLARE(exynos8855_cmu_top, "samsung,exynos8855-cmu-top", > + exynos8855_cmu_top_init); > + > +/* ---- CMU_PERIC --------------------------------------------------------- */ > + > +/* Register Offset definitions for CMU_PERIC (0x15400000) */ > +#define CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_IP_USER 0x600 > +#define CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_MMC_CARD_USER 0x610 > +#define CMU_PERIC_PLL_CON0_MUX_CLKCMU_PERIC_NOC_USER 0x620 > +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_I2C 0x1000 > +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_UART_DBG 0x1004 > +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI00 0x1008 > +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI01 0x100c > +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI02 0x1010 > +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI03 0x1014 > +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI04 0x1018 > +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI09_USI_OIS 0x101c > +#define CMU_PERIC_CLK_CON_MUX_CLK_PERIC_USI10_USI_OIS 0x1020 > +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_NOCP 0x1800 > +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_UART_DBG 0x1804 > +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI00_USI 0x1808 > +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI01_USI 0x180c > +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI02_USI 0x1810 > +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI03_USI 0x1814 > +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI04_USI 0x1818 > +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI09_USI_OIS 0x181c > +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI10_USI_OIS 0x1820 > +#define CMU_PERIC_CLK_CON_DIV_CLK_PERIC_USI_I2C 0x1824 > +#define CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_CMU_PERIC_IPCLKPORT_PCLK 0x2004 > +#define CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_SYSREG_PERIC_IPCLKPORT_PCLK 0x2060 > +#define CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_UART_DBG_IPCLKPORT_PCLK 0x2064 > +#define CMU_PERIC_CLK_CON_GAT_BLK_PERIC_UID_USI00_USI_IPCLKPORT_PCLK 0x206c > +#define CMU_PERIC_CONTROLLER_OPTION0_CMU_CTRL 0x800 > + If you don't define all registers (like QCH, etc.) in the CMUs that can be powered off, enabling power domains on this SoC might cause you to lose state configured by the bootloader (and quite possibly also suffer weird hard to debug timing/clock issues when enabling power management). Since auto clock mode is now used (and QCH registers are used by auto mode), I think it makes sense to define all the CMU registers that need their state preserved here. Thanks, Peter ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <CGME20261113104853epcas5p175c566a1ced2547e533c21b21e60e993@epcas5p1.samsung.com>]
* [PATCH v3 08/14 RESEND] clk: samsung: exynos8855: add block peris clock support [not found] ` <CGME20261113104853epcas5p175c566a1ced2547e533c21b21e60e993@epcas5p1.samsung.com> @ 2026-11-13 11:06 ` Raghav Sharma 0 siblings, 0 replies; 21+ messages in thread From: Raghav Sharma @ 2026-11-13 11:06 UTC (permalink / raw) To: krzk, s.nawrocki, cw00.choi, peter.griffin, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, raghav.s Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy Register compatible and cmu_info data to support clocks. CMU_PERIS, this provides clocks for PERIS Co-developed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Raghav Sharma <raghav.s@samsung.com> --- drivers/clk/samsung/clk-exynos8855.c | 97 ++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos8855.c b/drivers/clk/samsung/clk-exynos8855.c index dcf58f2459b0..12b5ae54b560 100644 --- a/drivers/clk/samsung/clk-exynos8855.c +++ b/drivers/clk/samsung/clk-exynos8855.c @@ -18,7 +18,9 @@ /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP (CLKCMU_DOUT_G3D_HTU + 1) #define CLKS_NR_PERIC (CLK_GOUT_USI_PERIC + 1) +#define CLKS_NR_PERIS (CLK_GOUT_WDT1_PERIS + 1) +#define EXYNOS8855_PERIS_GATE_DBG_OFFSET 0x2004 #define EXYNOS8855_PERIC_GATE_DBG_OFFSET 0x2024 #define EXYNOS8855_TOP_GATE_DBG_OFFSET 0x20A0 @@ -1092,6 +1094,98 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = { .memclk_offset = EXYNOS8855_MEMCLK_OFFSET, }; +/* ---- CMU_PERIS --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIS (0x10030000) */ +#define CMU_PERIS_PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER 0x600 +#define CMU_PERIS_CLK_CON_MUX_CLK_PERIS_GIC 0x1000 +#define CMU_PERIS_PLL_CON0_MUX_CLK_PERIS_GIC_USER 0x610 +#define CMU_PERIS_CLK_CON_DIV_CLK_PERIS_NOCP 0x1800 +#define CMU_PERIS_CLK_CON_DIV_CLK_PERIS_OTP 0x1804 +#define CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_CMU_PERIS_IPCLKPORT_PCLK 0x201c +#define CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x2040 +#define CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK 0x2048 +#define CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK 0x204c +#define CMU_PERIS_CONTROLLER_OPTION0_CMU_CTRL 0x800 + +static const unsigned long peris_clk_regs[] __initconst = { + CMU_PERIS_PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER, + CMU_PERIS_CLK_CON_MUX_CLK_PERIS_GIC, + CMU_PERIS_PLL_CON0_MUX_CLK_PERIS_GIC_USER, + CMU_PERIS_CLK_CON_DIV_CLK_PERIS_NOCP, + CMU_PERIS_CLK_CON_DIV_CLK_PERIS_OTP, + CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_CMU_PERIS_IPCLKPORT_PCLK, + CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK, + CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK, + CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK, + CMU_PERIS_CONTROLLER_OPTION0_CMU_CTRL, +}; + +/* List of parent clocks for Muxes in CMU_PERIS */ +PNAME(mout_clkcmu_peris_noc_user_p) = { "oscclk", "dout_clkcmu_peris_noc" }; +PNAME(mout_clk_peris_gic_p) = { "oscclk", "mout_clkcmu_peris_gic_user" }; +PNAME(mout_clkcmu_peris_gic_user_p) = { "oscclk", "dout_clkcmu_peris_gic" }; + +static const struct samsung_mux_clock peris_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIS_NOC_USER, "mout_clkcmu_peris_noc_user", + mout_clkcmu_peris_noc_user_p, CMU_PERIS_PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER, 4, 1), + MUX(CLK_MOUT_PERIS_GIC, "mout_clk_peris_gic", + mout_clk_peris_gic_p, CMU_PERIS_CLK_CON_MUX_CLK_PERIS_GIC, 0, 1), + MUX(CLK_MOUT_PERIS_GIC_USER, "mout_clkcmu_peris_gic_user", + mout_clkcmu_peris_gic_user_p, CMU_PERIS_PLL_CON0_MUX_CLK_PERIS_GIC_USER, 4, 1), +}; + +static const struct samsung_div_clock peris_div_clks[] __initconst = { + DIV(CLK_DOUT_PERIS_NOCP, "dout_clkcmu_peris_nocp", + "mout_clkcmu_peris_noc_user", CMU_PERIS_CLK_CON_DIV_CLK_PERIS_NOCP, + 0, 4), + DIV(CLK_DOUT_PERIS_OTP, "dout_clkcmu_peris_otp", + "oscclk", CMU_PERIS_CLK_CON_DIV_CLK_PERIS_OTP, + 0, 4), +}; + +static const struct samsung_gate_clock peris_gate_clks[] __initconst = { + GATE(CLK_GOUT_CMU_PERIS, "gout_cmu_peris", + "dout_clkcmu_peris_nocp", + CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_CMU_PERIS_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_SYSREG_PERIS, "gout_sysreg_peris", + "dout_clkcmu_peris_nocp", + CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_WDT0_PERIS, "gout_wdt0_peris", + "dout_clkcmu_peris_nocp", + CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_WDT1_PERIS, "gout_wdt1_peris", + "dout_clkcmu_peris_nocp", + CMU_PERIS_CLK_CON_GAT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK, + 21, 0, 0), +}; + +static const unsigned long dcrg_sysreg[] __initconst = { + EXYNOS8855_DRCG_EN_OFFSET, +}; + +static const struct samsung_cmu_info peris_cmu_info __initconst = { + .mux_clks = peris_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), + .div_clks = peris_div_clks, + .nr_div_clks = ARRAY_SIZE(peris_div_clks), + .gate_clks = peris_gate_clks, + .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), + .nr_clk_ids = CLKS_NR_PERIS, + .clk_regs = peris_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), + .sysreg_clk_regs = dcrg_sysreg, + .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_sysreg), + .clk_name = "bus", + .auto_clock_gate = true, + .gate_dbg_offset = EXYNOS8855_PERIS_GATE_DBG_OFFSET, + .option_offset = CMU_PERIS_CONTROLLER_OPTION0_CMU_CTRL, + .drcg_offset = EXYNOS8855_DRCG_EN_OFFSET, +}; + static int __init exynos8855_cmu_probe(struct platform_device *pdev) { const struct samsung_cmu_info *info; @@ -1107,6 +1201,9 @@ static const struct of_device_id exynos8855_cmu_of_match[] = { { .compatible = "samsung,exynos8855-cmu-peric", .data = &peric_cmu_info, + }, { + .compatible = "samsung,exynos8855-cmu-peris", + .data = &peris_cmu_info, }, { .compatible = "samsung,exynos8855-cmu-top", .data = &top_cmu_info, -- 2.34.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <CGME20261113104855epcas5p1ed56e1444542349a8f2839cf27df3d60@epcas5p1.samsung.com>]
* [PATCH v3 09/14 RESEND] clk: samsung: exynos8855: add block hsi clock support [not found] ` <CGME20261113104855epcas5p1ed56e1444542349a8f2839cf27df3d60@epcas5p1.samsung.com> @ 2026-11-13 11:06 ` Raghav Sharma 0 siblings, 0 replies; 21+ messages in thread From: Raghav Sharma @ 2026-11-13 11:06 UTC (permalink / raw) To: krzk, s.nawrocki, cw00.choi, peter.griffin, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, raghav.s Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy Register compatible and cmu_info data to support clocks. CMU_HSI, this provides clocks for HSI Co-developed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Raghav Sharma <raghav.s@samsung.com> --- drivers/clk/samsung/clk-exynos8855.c | 74 ++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos8855.c b/drivers/clk/samsung/clk-exynos8855.c index 12b5ae54b560..0be1cefadb51 100644 --- a/drivers/clk/samsung/clk-exynos8855.c +++ b/drivers/clk/samsung/clk-exynos8855.c @@ -19,7 +19,9 @@ #define CLKS_NR_TOP (CLKCMU_DOUT_G3D_HTU + 1) #define CLKS_NR_PERIC (CLK_GOUT_USI_PERIC + 1) #define CLKS_NR_PERIS (CLK_GOUT_WDT1_PERIS + 1) +#define CLKS_NR_HSI (CLK_GOUT_UFS_EMBD_UNIPRO_HSI + 1) +#define EXYNOS8855_HSI_GATE_DBG_OFFSET 0x2000 #define EXYNOS8855_PERIS_GATE_DBG_OFFSET 0x2004 #define EXYNOS8855_PERIC_GATE_DBG_OFFSET 0x2024 #define EXYNOS8855_TOP_GATE_DBG_OFFSET 0x20A0 @@ -1186,6 +1188,75 @@ static const struct samsung_cmu_info peris_cmu_info __initconst = { .drcg_offset = EXYNOS8855_DRCG_EN_OFFSET, }; +/* ---- CMU_HSI --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_HSI (0x17000000) */ +#define CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_NOC_USER 0x600 +#define CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER 0x610 +#define CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_CMU_HSI_IPCLKPORT_PCLK 0x2000 +#define CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK 0x2038 +#define CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK 0x203c +#define CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO 0x2058 +#define CMU_HSI_CONTROLLER_OPTION0_CMU_CTRL 0x800 + +static const unsigned long hsi_clk_regs[] __initconst = { + CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_NOC_USER, + CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER, + CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_CMU_HSI_IPCLKPORT_PCLK, + CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK, + CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK, + CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, + CMU_HSI_CONTROLLER_OPTION0_CMU_CTRL, +}; + +/* List of parent clocks for Muxes in CMU_HSI */ +PNAME(mout_clkcmu_hsi_noc_user_p) = { "oscclk", "dout_clkcmu_hsi_noc" }; +PNAME(mout_clkcmu_hsi_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_hsi_ufs_embd" }; + +static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { + MUX(CLK_MOUT_HSI_NOC_USER, "mout_clkcmu_hsi_noc_user", + mout_clkcmu_hsi_noc_user_p, CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_NOC_USER, 4, 1), + MUX(CLK_MOUT_HSI_UFS_EMBD_USER, "mout_clkcmu_hsi_ufs_embd_user", + mout_clkcmu_hsi_ufs_embd_user_p, CMU_HSI_PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER, 4, 1), +}; + +static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { + GATE(CLK_GOUT_CMU_HSI, "gout_cmu_hsi", + "mout_clkcmu_hsi_noc_user", + CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_CMU_HSI_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_SYSREG_HSI, "gout_sysreg_hsi", + "mout_clkcmu_hsi_noc_user", + CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_UFS_EMBD_ACLK_HSI, "gout_ufs_embd_aclk_hsi", + "mout_clkcmu_hsi_noc_user", + CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK, + 21, 0, 0), + GATE(CLK_GOUT_UFS_EMBD_UNIPRO_HSI, "gout_ufs_embd_unipro_hsi", + "mout_clkcmu_hsi_ufs_embd_user", + CMU_HSI_CLK_CON_GAT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, + 21, 0, 0), +}; + +static const struct samsung_cmu_info hsi_cmu_info __initconst = { + .mux_clks = hsi_mux_clks, + .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks), + .gate_clks = hsi_gate_clks, + .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks), + .nr_clk_ids = CLKS_NR_HSI, + .clk_regs = hsi_clk_regs, + .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs), + .sysreg_clk_regs = dcrg_memclk_sysreg, + .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg), + .clk_name = "bus", + .auto_clock_gate = true, + .gate_dbg_offset = EXYNOS8855_HSI_GATE_DBG_OFFSET, + .option_offset = CMU_HSI_CONTROLLER_OPTION0_CMU_CTRL, + .drcg_offset = EXYNOS8855_DRCG_EN_OFFSET, + .memclk_offset = EXYNOS8855_MEMCLK_OFFSET, +}; + static int __init exynos8855_cmu_probe(struct platform_device *pdev) { const struct samsung_cmu_info *info; @@ -1199,6 +1270,9 @@ static int __init exynos8855_cmu_probe(struct platform_device *pdev) static const struct of_device_id exynos8855_cmu_of_match[] = { { + .compatible = "samsung,exynos8855-cmu-hsi", + .data = &hsi_cmu_info, + }, { .compatible = "samsung,exynos8855-cmu-peric", .data = &peric_cmu_info, }, { -- 2.34.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <CGME20261113104858epcas5p47fb0f4e46302dfe01070f4cd298870ca@epcas5p4.samsung.com>]
* [PATCH v3 10/14 RESEND] clk: samsung: exynos8855: add block usb clock support [not found] ` <CGME20261113104858epcas5p47fb0f4e46302dfe01070f4cd298870ca@epcas5p4.samsung.com> @ 2026-11-13 11:06 ` Raghav Sharma 0 siblings, 0 replies; 21+ messages in thread From: Raghav Sharma @ 2026-11-13 11:06 UTC (permalink / raw) To: krzk, s.nawrocki, cw00.choi, peter.griffin, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, raghav.s Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy Register compatible and cmu_info data to support clocks. CMU_USB, this provides clocks for USB Co-developed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Raghav Sharma <raghav.s@samsung.com> --- drivers/clk/samsung/clk-exynos8855.c | 77 ++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos8855.c b/drivers/clk/samsung/clk-exynos8855.c index 0be1cefadb51..87c616c8487e 100644 --- a/drivers/clk/samsung/clk-exynos8855.c +++ b/drivers/clk/samsung/clk-exynos8855.c @@ -20,11 +20,13 @@ #define CLKS_NR_PERIC (CLK_GOUT_USI_PERIC + 1) #define CLKS_NR_PERIS (CLK_GOUT_WDT1_PERIS + 1) #define CLKS_NR_HSI (CLK_GOUT_UFS_EMBD_UNIPRO_HSI + 1) +#define CLKS_NR_USB (CLK_GOUT_SYSREG_USB + 1) #define EXYNOS8855_HSI_GATE_DBG_OFFSET 0x2000 #define EXYNOS8855_PERIS_GATE_DBG_OFFSET 0x2004 #define EXYNOS8855_PERIC_GATE_DBG_OFFSET 0x2024 #define EXYNOS8855_TOP_GATE_DBG_OFFSET 0x20A0 +#define EXYNOS8855_USB_GATE_DBG_OFFSET 0x2004 #define EXYNOS8855_DRCG_EN_OFFSET 0x104 #define EXYNOS8855_MEMCLK_OFFSET 0x108 @@ -1257,6 +1259,78 @@ static const struct samsung_cmu_info hsi_cmu_info __initconst = { .memclk_offset = EXYNOS8855_MEMCLK_OFFSET, }; +/* ---- CMU_USB --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_USB (0x13000000) */ +#define CMU_USB_PLL_CON0_MUX_CLKCMU_USB_NOC_USER 0x600 +#define CMU_USB_PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER 0x610 +#define CMU_USB_CLK_CON_MUX_CLK_USB_USB20DRD 0x1000 +#define CMU_USB_CLK_CON_DIV_CLK_USB_NOC_DIV3 0x1800 +#define CMU_USB_CLK_CON_GAT_BLK_USB_UID_CMU_USB_IPCLKPORT_PCLK 0x2000 +#define CMU_USB_CLK_CON_GAT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK 0x2030 +#define CMU_USB_CONTROLLER_OPTION0_CMU_CTRL 0x800 + +static const unsigned long usb_clk_regs[] __initconst = { + CMU_USB_PLL_CON0_MUX_CLKCMU_USB_NOC_USER, + CMU_USB_PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER, + CMU_USB_CLK_CON_MUX_CLK_USB_USB20DRD, + CMU_USB_CLK_CON_DIV_CLK_USB_NOC_DIV3, + CMU_USB_CLK_CON_GAT_BLK_USB_UID_CMU_USB_IPCLKPORT_PCLK, + CMU_USB_CLK_CON_GAT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK, + CMU_USB_CONTROLLER_OPTION0_CMU_CTRL, +}; + +/* List of parent clocks for Muxes in CMU_USB */ +PNAME(mout_clkcmu_usb_noc_user_p) = { "oscclk", "dout_clkcmu_usb_noc" }; +PNAME(mout_clkcmu_usb_usb20drd_user_p) = { "oscclk", "dout_clkcmu_usb_usb20drd" }; +PNAME(mout_clk_usb_usb20drd_p) = { "oscclk_usb_link", "mout_clkcmu_usb_usb20drd_user" }; + +static const struct samsung_mux_clock usb_mux_clks[] __initconst = { + MUX(CLK_MOUT_USB_NOC_USER, "mout_clkcmu_usb_noc_user", + mout_clkcmu_usb_noc_user_p, CMU_USB_PLL_CON0_MUX_CLKCMU_USB_NOC_USER, 4, 1), + MUX(CLK_MOUT_USB_USB20DRD_USER, "mout_clkcmu_usb_usb20drd_user", + mout_clkcmu_usb_usb20drd_user_p, CMU_USB_PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER, 4, 1), + MUX(CLK_MOUT_USB_USB20DRD, "mout_clk_usb_usb20drd", + mout_clk_usb_usb20drd_p, CMU_USB_CLK_CON_MUX_CLK_USB_USB20DRD, 0, 1), +}; + +static const struct samsung_div_clock usb_div_clks[] __initconst = { + DIV(CLK_DOUT_USB_NOC_DIV3, "dout_clkcmu_usb_noc_div3", + "mout_clkcmu_usb_noc_user", CMU_USB_CLK_CON_DIV_CLK_USB_NOC_DIV3, + 0, 4), +}; + +static const struct samsung_gate_clock usb_gate_clks[] __initconst = { + GATE(CLK_GOUT_CMU_USB, "gout_cmu_usb", + "mout_clkcmu_usb_noc_user", + CMU_USB_CLK_CON_GAT_BLK_USB_UID_CMU_USB_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_SYSREG_USB, "gout_sysreg_usb", + "mout_clkcmu_usb_noc_user", + CMU_USB_CLK_CON_GAT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK, + 21, 0, 0), +}; + +static const struct samsung_cmu_info usb_cmu_info __initconst = { + .mux_clks = usb_mux_clks, + .nr_mux_clks = ARRAY_SIZE(usb_mux_clks), + .div_clks = usb_div_clks, + .nr_div_clks = ARRAY_SIZE(usb_div_clks), + .gate_clks = usb_gate_clks, + .nr_gate_clks = ARRAY_SIZE(usb_gate_clks), + .nr_clk_ids = CLKS_NR_USB, + .clk_regs = usb_clk_regs, + .nr_clk_regs = ARRAY_SIZE(usb_clk_regs), + .sysreg_clk_regs = dcrg_memclk_sysreg, + .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg), + .clk_name = "bus", + .auto_clock_gate = true, + .gate_dbg_offset = EXYNOS8855_USB_GATE_DBG_OFFSET, + .option_offset = CMU_USB_CONTROLLER_OPTION0_CMU_CTRL, + .drcg_offset = EXYNOS8855_DRCG_EN_OFFSET, + .memclk_offset = EXYNOS8855_MEMCLK_OFFSET, +}; + static int __init exynos8855_cmu_probe(struct platform_device *pdev) { const struct samsung_cmu_info *info; @@ -1281,6 +1355,9 @@ static const struct of_device_id exynos8855_cmu_of_match[] = { }, { .compatible = "samsung,exynos8855-cmu-top", .data = &top_cmu_info, + }, { + .compatible = "samsung,exynos8855-cmu-usb", + .data = &usb_cmu_info, }, { } }; -- 2.34.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <CGME20261113104901epcas5p26c1b8e9a324f133216b7980ac7ded44a@epcas5p2.samsung.com>]
* [PATCH v3 11/14 RESEND] arm64: dts: exynos8855: add cmu_top & cmu_peric clock DT nodes [not found] ` <CGME20261113104901epcas5p26c1b8e9a324f133216b7980ac7ded44a@epcas5p2.samsung.com> @ 2026-11-13 11:06 ` Raghav Sharma 0 siblings, 0 replies; 21+ messages in thread From: Raghav Sharma @ 2026-11-13 11:06 UTC (permalink / raw) To: krzk, s.nawrocki, cw00.choi, peter.griffin, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, raghav.s Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy Add required dt node for cmu_top & cmu_peric block. This also add sysreg_peric node. sysreg_peric contains DRCG and MEMCLK SFRs bits which are used in clock driver. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Raghav Sharma <raghav.s@samsung.com> --- arch/arm64/boot/dts/exynos/exynos8855.dtsi | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi index 0333b80eba84..2e5dc79d66bc 100644 --- a/arch/arm64/boot/dts/exynos/exynos8855.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi @@ -10,6 +10,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/samsung,exynos8855.h> / { compatible = "samsung,exynos8855"; @@ -170,12 +171,43 @@ pinctrl_cmgp: pinctrl@12030000 { interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; }; + cmu_top: clock-controller@13900000 { + compatible = "samsung,exynos8855-cmu-top"; + reg = <0x13900000 0x10000>; + #clock-cells = <1>; + clocks = <&oscclk>; + clock-names = "oscclk"; + }; + pinctrl_usi: pinctrl@15030000 { compatible = "samsung,exynos8855-pinctrl"; reg = <0x15030000 0x1000>; interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; }; + cmu_peric: clock-controller@15400000 { + compatible = "samsung,exynos8855-cmu-peric"; + reg = <0x15400000 0x10000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLKCMU_DOUT_PERIC_NOC>, + <&cmu_top CLKCMU_DOUT_PERIC_MMC_CARD>, + <&cmu_top CLKCMU_DOUT_PERIC_IP>; + clock-names = "oscclk", + "bus", + "mmc_card", + "ip"; + samsung,sysreg = <&sysreg_peric>; + }; + + sysreg_peric: syscon@15420000 { + compatible = "samsung,exynos8855-peric-sysreg", + "syscon"; + reg = <0x15420000 0x10000>; + clocks = <&cmu_peric CLK_GOUT_SYSREG_PERIC>; + }; + pinctrl_peric: pinctrl@15440000 { compatible = "samsung,exynos8855-pinctrl"; reg = <0x15440000 0x1000>; -- 2.34.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <CGME20261113104904epcas5p1546fd543fad42a61f1a70d4fd55ac833@epcas5p1.samsung.com>]
* [PATCH v3 12/14 RESEND] arm64: dts: exynos8855: add cmu_peris clock DT nodes [not found] ` <CGME20261113104904epcas5p1546fd543fad42a61f1a70d4fd55ac833@epcas5p1.samsung.com> @ 2026-11-13 11:06 ` Raghav Sharma 0 siblings, 0 replies; 21+ messages in thread From: Raghav Sharma @ 2026-11-13 11:06 UTC (permalink / raw) To: krzk, s.nawrocki, cw00.choi, peter.griffin, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, raghav.s Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy Add required dt node for cmu_peris block. Also add sysreg_peris node. sysreg_peris contains DRCG SFRs bits which are used in clock driver. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Raghav Sharma <raghav.s@samsung.com> --- arch/arm64/boot/dts/exynos/exynos8855.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi index 2e5dc79d66bc..b461de6a7548 100644 --- a/arch/arm64/boot/dts/exynos/exynos8855.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi @@ -146,6 +146,27 @@ soc: soc@0 { #size-cells = <1>; ranges = <0x0 0x0 0x0 0x20000000>; + sysreg_peris: syscon@10020000 { + compatible = "samsung,exynos8855-peris-sysreg", + "syscon"; + reg = <0x10020000 0x10000>; + clocks = <&cmu_peris CLK_GOUT_SYSREG_PERIS>; + }; + + cmu_peris: clock-controller@10030000 { + compatible = "samsung,exynos8855-cmu-peris"; + reg = <0x10030000 0x10000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLKCMU_DOUT_PERIS_GIC>, + <&cmu_top CLKCMU_DOUT_PERIS_NOC>; + clock-names = "oscclk", + "gic", + "bus"; + samsung,sysreg = <&sysreg_peris>; + }; + gic: interrupt-controller@10200000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; -- 2.34.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <CGME20261113104906epcas5p462308ef9eec80f8b7a5f81b64e72b24d@epcas5p4.samsung.com>]
* [PATCH v3 13/14 RESEND] arm64: dts: exynos8855: add cmu_hsi clock DT nodes [not found] ` <CGME20261113104906epcas5p462308ef9eec80f8b7a5f81b64e72b24d@epcas5p4.samsung.com> @ 2026-11-13 11:06 ` Raghav Sharma 0 siblings, 0 replies; 21+ messages in thread From: Raghav Sharma @ 2026-11-13 11:06 UTC (permalink / raw) To: krzk, s.nawrocki, cw00.choi, peter.griffin, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, raghav.s Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy Add required dt node for cmu_hsi block, while at it add sysreg_hsi node which contians bits for DRCG and MEMCLK which are used by clock driver Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Raghav Sharma <raghav.s@samsung.com> --- arch/arm64/boot/dts/exynos/exynos8855.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi index b461de6a7548..3dd7a4c4c609 100644 --- a/arch/arm64/boot/dts/exynos/exynos8855.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi @@ -241,6 +241,27 @@ pinctrl_pericmmc: pinctrl@154f0000 { interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; }; + cmu_hsi: clock-controller@17000000 { + compatible = "samsung,exynos8855-cmu-hsi"; + reg = <0x17000000 0x10000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLKCMU_DOUT_HSI_NOC>, + <&cmu_top CLKCMU_DOUT_HSI_UFS_EMBD>; + clock-names = "oscclk", + "bus", + "ufs_embd"; + samsung,sysreg = <&sysreg_hsi>; + }; + + sysreg_hsi: syscon@17020000 { + compatible = "samsung,exynos8855-hsi-sysreg", + "syscon"; + reg = <0x17020000 0x10000>; + clocks = <&cmu_hsi CLK_GOUT_SYSREG_HSI>; + }; + pinctrl_hsi_ufs: pinctrl@17040000 { compatible = "samsung,exynos8855-pinctrl"; reg = <0x17040000 0x1000>; -- 2.34.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
[parent not found: <CGME20261113104909epcas5p1d1b81b4e800e8a1d1cf830f21e52499a@epcas5p1.samsung.com>]
* [PATCH v3 14/14 RESEND] arm64: dts: exynos8855: add cmu_usb clock DT nodes [not found] ` <CGME20261113104909epcas5p1d1b81b4e800e8a1d1cf830f21e52499a@epcas5p1.samsung.com> @ 2026-11-13 11:06 ` Raghav Sharma 0 siblings, 0 replies; 21+ messages in thread From: Raghav Sharma @ 2026-11-13 11:06 UTC (permalink / raw) To: krzk, s.nawrocki, cw00.choi, peter.griffin, alim.akhtar, sboyd, bmasney+clk, jbrunet+clk, robh, conor+dt, raghav.s Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel, is.gandhi, ts.amit, pokala.reddy Add required dt node for cmu_usb block, while at this add sysreg_usb which contains bits for DRCG and MEMCLK which are used by clk driver Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Raghav Sharma <raghav.s@samsung.com> --- arch/arm64/boot/dts/exynos/exynos8855.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi index 3dd7a4c4c609..dcf1e58c6367 100644 --- a/arch/arm64/boot/dts/exynos/exynos8855.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi @@ -192,6 +192,27 @@ pinctrl_cmgp: pinctrl@12030000 { interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; }; + cmu_usb: clock-controller@13000000 { + compatible = "samsung,exynos8855-cmu-usb"; + reg = <0x13000000 0x10000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLKCMU_DOUT_USB_NOC>, + <&cmu_top CLKCMU_DOUT_USB_USB20DRD>; + clock-names = "oscclk", + "bus", + "usb20drd"; + samsung,sysreg = <&sysreg_usb>; + }; + + sysreg_usb: syscon@13020000 { + compatible = "samsung,exynos8855-usb-sysreg", + "syscon"; + reg = <0x13020000 0x10000>; + clocks = <&cmu_usb CLK_GOUT_SYSREG_USB>; + }; + cmu_top: clock-controller@13900000 { compatible = "samsung,exynos8855-cmu-top"; reg = <0x13900000 0x10000>; -- 2.34.1 ^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2026-11-13 12:06 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
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[not found] <CGME20261113104829epcas5p13695795bc337b89816b05eec610a0dba@epcas5p1.samsung.com>
2026-11-13 11:05 ` [PATCH v3 00/14 RESEND] Add clock support for Exynos8855 SoC Raghav Sharma
[not found] ` <CGME20261113104832epcas5p4e1e9a3dedeb0c9c60cb80c23eb5d930d@epcas5p4.samsung.com>
2026-11-13 11:05 ` [PATCH v3 01/14 RESEND] dt-bindings: soc: samsung: Exynos8855 SYSREG compatibles Raghav Sharma
2026-11-13 10:57 ` Peter Griffin
[not found] ` <CGME20261113104835epcas5p4771d9933265138321769ebe010ee7334@epcas5p4.samsung.com>
2026-11-13 11:06 ` [PATCH v3 02/14 RESEND] dt-bindings: clock: exynos8855: add top & peric clock definitions Raghav Sharma
2026-11-13 11:01 ` Peter Griffin
[not found] ` <CGME20261113104838epcas5p2623c7a05b6163954e13e98367063e7d4@epcas5p2.samsung.com>
2026-11-13 11:06 ` [PATCH v3 03/14 RESEND] dt-bindings: clock: exynos8855: add peris " Raghav Sharma
2026-11-13 11:25 ` Peter Griffin
[not found] ` <CGME20261113104841epcas5p2823126ce22f44cc98fcbdf94403c32e3@epcas5p2.samsung.com>
2026-11-13 11:06 ` [PATCH v3 04/14 RESEND] dt-bindings: clock: exynos8855: add hsi " Raghav Sharma
2026-11-13 11:02 ` Peter Griffin
[not found] ` <CGME20261113104844epcas5p4c1cb0c31de8b5b445f7f0060f81cf753@epcas5p4.samsung.com>
2026-11-13 11:06 ` [PATCH v3 05/14 RESEND] dt-bindings: clock: exynos8855: add usb " Raghav Sharma
2026-11-13 11:03 ` Peter Griffin
[not found] ` <CGME20261113104847epcas5p1d970255218f1ca78b19690bfd097f303@epcas5p1.samsung.com>
2026-11-13 11:06 ` [PATCH v3 06/14 RESEND] clk: samsung: clk-pll: Add support for pll_4313 Raghav Sharma
[not found] ` <CGME20261113104850epcas5p4ef9292af100475b1f12a2601bf5e1a84@epcas5p4.samsung.com>
2026-11-13 11:06 ` [PATCH v3 07/14 RESEND] clk: samsung: exynos8855: add block top and peric clock support Raghav Sharma
2026-11-13 12:06 ` Peter Griffin
[not found] ` <CGME20261113104853epcas5p175c566a1ced2547e533c21b21e60e993@epcas5p1.samsung.com>
2026-11-13 11:06 ` [PATCH v3 08/14 RESEND] clk: samsung: exynos8855: add block peris " Raghav Sharma
[not found] ` <CGME20261113104855epcas5p1ed56e1444542349a8f2839cf27df3d60@epcas5p1.samsung.com>
2026-11-13 11:06 ` [PATCH v3 09/14 RESEND] clk: samsung: exynos8855: add block hsi " Raghav Sharma
[not found] ` <CGME20261113104858epcas5p47fb0f4e46302dfe01070f4cd298870ca@epcas5p4.samsung.com>
2026-11-13 11:06 ` [PATCH v3 10/14 RESEND] clk: samsung: exynos8855: add block usb " Raghav Sharma
[not found] ` <CGME20261113104901epcas5p26c1b8e9a324f133216b7980ac7ded44a@epcas5p2.samsung.com>
2026-11-13 11:06 ` [PATCH v3 11/14 RESEND] arm64: dts: exynos8855: add cmu_top & cmu_peric clock DT nodes Raghav Sharma
[not found] ` <CGME20261113104904epcas5p1546fd543fad42a61f1a70d4fd55ac833@epcas5p1.samsung.com>
2026-11-13 11:06 ` [PATCH v3 12/14 RESEND] arm64: dts: exynos8855: add cmu_peris " Raghav Sharma
[not found] ` <CGME20261113104906epcas5p462308ef9eec80f8b7a5f81b64e72b24d@epcas5p4.samsung.com>
2026-11-13 11:06 ` [PATCH v3 13/14 RESEND] arm64: dts: exynos8855: add cmu_hsi " Raghav Sharma
[not found] ` <CGME20261113104909epcas5p1d1b81b4e800e8a1d1cf830f21e52499a@epcas5p1.samsung.com>
2026-11-13 11:06 ` [PATCH v3 14/14 RESEND] arm64: dts: exynos8855: add cmu_usb " Raghav Sharma
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