[PATCH net 0/3] net: dsa: lantiq_gswip: SGMII/2500BASE-X and flow-control fixes

[PATCH net 0/3] net: dsa: lantiq_gswip: SGMII/2500BASE-X and flow-control fixes

[Jan Havran (Advantech Czech)]

This series fixes three issues in the lantiq_gswip / mxl-gsw1xx DSA driver
found while bringing up a MaxLinear GSW145 over SGMII on a Marvell
Armada 7040 board, with the switch CPU port running 2500BASE-X and the
user ports at 1000BASE-T.

Patch 1 reorders the SerDes NCO clock-rate setup ahead of the SGMII shell
reset. Without it, only the rate the switch was left at by the straps or
the boot loader links up; the other rate comes up but forwards no traffic.

Patch 2 adds the missing SPEED_2500 case to gswip_port_set_speed(); without
it the CPU port was forced to 10 Mbps at 2.5G link-up.

Patch 3 corrects the GSWIP_MDIO_PHY_FCONTX_EN field value (a typo present
since the original vrx200 driver).

Tested on GSW145 hardware only. The register values are backed by the
public GSW145 data sheet and by the driver's own field encoding; the
xRX200/xRX300 data sheets are not public.

Jan Havran (Advantech Czech) (3):
  net: dsa: mxl-gsw1xx: set SerDes NCO rate before SGMII reset
  net: dsa: lantiq_gswip: handle SPEED_2500 in gswip_port_set_speed()
  net: dsa: lantiq_gswip: fix GSWIP_MDIO_PHY_FCONTX_EN value

 drivers/net/dsa/lantiq/lantiq_gswip.h        |  2 +-
 drivers/net/dsa/lantiq/lantiq_gswip_common.c |  1 +
 drivers/net/dsa/lantiq/mxl-gsw1xx.c          | 29 ++++++++++----------
 3 files changed, 17 insertions(+), 15 deletions(-)


base-commit: 38b6be101006d3e7af972999f45d4f1e8250587a
-- 
2.39.5

[PATCH net 1/3] net: dsa: mxl-gsw1xx: set SerDes NCO rate before SGMII reset

[Jan Havran (Advantech Czech)]

gsw1xx_pcs_config() releases the SGMII shell from reset via
gsw1xx_pcs_reset() and only afterwards programs NCO_CTRL to select the
SerDes clock rate (1G NCO1 vs 2.5G NCO2). The chip boot loader uses the
other order: NCO_CTRL -> RST_REQ -> SGMII_PHY_HWBU_CTRL (GSW145 data
sheet, section 3.2.8, table 13).

Program NCO_CTRL before gsw1xx_pcs_reset() to follow that order. On an
Armada 7040 board driving a GSW145 whose switch comes up at 2.5G (pin strap
PS_SUBTYPE_MD[2] = 1, pin LED42 / PS1 bit 14; GSW145 data sheet tables 23
and 25), a 1 Gbps SGMII link only carried traffic with this change. It
matters when the rate the switch is left at - by the straps or by the boot
loader - differs from the rate the driver selects, which is likely why it
has not been seen before.

Fixes: 22335939ec90 ("net: dsa: add driver for MaxLinear GSW1xx switch family")
Signed-off-by: Jan Havran (Advantech Czech) <havran.jan@email.cz>
---
 drivers/net/dsa/lantiq/mxl-gsw1xx.c | 29 +++++++++++++++--------------
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.c b/drivers/net/dsa/lantiq/mxl-gsw1xx.c
index a1104b2f92a92..b8d8fefaa3a15 100644
--- a/drivers/net/dsa/lantiq/mxl-gsw1xx.c
+++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.c
@@ -352,8 +352,22 @@ static int gsw1xx_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
 	/* mark PCS configuration as incomplete */
 	priv->tbi_interface = PHY_INTERFACE_MODE_NA;
 
-	if (!reconf)
+	if (!reconf) {
+		/* setup SerDes clock speed */
+		if (interface == PHY_INTERFACE_MODE_2500BASEX)
+			nco_ctrl = GSW1XX_SGMII_2G5 | GSW1XX_SGMII_2G5_NCO2;
+		else
+			nco_ctrl = GSW1XX_SGMII_1G | GSW1XX_SGMII_1G_NCO1;
+
+		ret = regmap_update_bits(priv->clk, GSW1XX_CLK_NCO_CTRL,
+					 GSW1XX_SGMII_HSP_MASK |
+					 GSW1XX_SGMII_SEL,
+					 nco_ctrl);
+		if (ret)
+			return ret;
+
 		ret = gsw1xx_pcs_reset(priv, interface);
+	}
 
 	if (ret)
 		return ret;
@@ -423,19 +437,6 @@ static int gsw1xx_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
 		return ret;
 
 	if (!reconf) {
-		/* setup SerDes clock speed */
-		if (interface == PHY_INTERFACE_MODE_2500BASEX)
-			nco_ctrl = GSW1XX_SGMII_2G5 | GSW1XX_SGMII_2G5_NCO2;
-		else
-			nco_ctrl = GSW1XX_SGMII_1G | GSW1XX_SGMII_1G_NCO1;
-
-		ret = regmap_update_bits(priv->clk, GSW1XX_CLK_NCO_CTRL,
-					 GSW1XX_SGMII_HSP_MASK |
-					 GSW1XX_SGMII_SEL,
-					 nco_ctrl);
-		if (ret)
-			return ret;
-
 		ret = gsw1xx_pcs_phy_xaui_write(priv, 0x30, 0x80);
 		if (ret)
 			return ret;
-- 
2.39.5

Re: [PATCH net 1/3] net: dsa: mxl-gsw1xx: set SerDes NCO rate before SGMII reset

[Maxime Chevallier]

Hi,

On 9/7/26 15:48, Jan Havran (Advantech Czech) wrote:
> gsw1xx_pcs_config() releases the SGMII shell from reset via
> gsw1xx_pcs_reset() and only afterwards programs NCO_CTRL to select the
> SerDes clock rate (1G NCO1 vs 2.5G NCO2). The chip boot loader uses the
> other order: NCO_CTRL -> RST_REQ -> SGMII_PHY_HWBU_CTRL (GSW145 data
> sheet, section 3.2.8, table 13).
> 
> Program NCO_CTRL before gsw1xx_pcs_reset() to follow that order. On an
> Armada 7040 board driving a GSW145 whose switch comes up at 2.5G (pin strap
> PS_SUBTYPE_MD[2] = 1, pin LED42 / PS1 bit 14; GSW145 data sheet tables 23
> and 25), a 1 Gbps SGMII link only carried traffic with this change. It
> matters when the rate the switch is left at - by the straps or by the boot
> loader - differs from the rate the driver selects, which is likely why it
> has not been seen before.
> 
> Fixes: 22335939ec90 ("net: dsa: add driver for MaxLinear GSW1xx switch family")
> Signed-off-by: Jan Havran (Advantech Czech) <havran.jan@email.cz>

Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>

Maxime

> ---
>  drivers/net/dsa/lantiq/mxl-gsw1xx.c | 29 +++++++++++++++--------------
>  1 file changed, 15 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.c b/drivers/net/dsa/lantiq/mxl-gsw1xx.c
> index a1104b2f92a92..b8d8fefaa3a15 100644
> --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.c
> +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.c
> @@ -352,8 +352,22 @@ static int gsw1xx_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
>  	/* mark PCS configuration as incomplete */
>  	priv->tbi_interface = PHY_INTERFACE_MODE_NA;
>  
> -	if (!reconf)
> +	if (!reconf) {
> +		/* setup SerDes clock speed */
> +		if (interface == PHY_INTERFACE_MODE_2500BASEX)
> +			nco_ctrl = GSW1XX_SGMII_2G5 | GSW1XX_SGMII_2G5_NCO2;
> +		else
> +			nco_ctrl = GSW1XX_SGMII_1G | GSW1XX_SGMII_1G_NCO1;
> +
> +		ret = regmap_update_bits(priv->clk, GSW1XX_CLK_NCO_CTRL,
> +					 GSW1XX_SGMII_HSP_MASK |
> +					 GSW1XX_SGMII_SEL,
> +					 nco_ctrl);
> +		if (ret)
> +			return ret;
> +
>  		ret = gsw1xx_pcs_reset(priv, interface);
> +	}
>  
>  	if (ret)
>  		return ret;
> @@ -423,19 +437,6 @@ static int gsw1xx_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
>  		return ret;
>  
>  	if (!reconf) {
> -		/* setup SerDes clock speed */
> -		if (interface == PHY_INTERFACE_MODE_2500BASEX)
> -			nco_ctrl = GSW1XX_SGMII_2G5 | GSW1XX_SGMII_2G5_NCO2;
> -		else
> -			nco_ctrl = GSW1XX_SGMII_1G | GSW1XX_SGMII_1G_NCO1;
> -
> -		ret = regmap_update_bits(priv->clk, GSW1XX_CLK_NCO_CTRL,
> -					 GSW1XX_SGMII_HSP_MASK |
> -					 GSW1XX_SGMII_SEL,
> -					 nco_ctrl);
> -		if (ret)
> -			return ret;
> -
>  		ret = gsw1xx_pcs_phy_xaui_write(priv, 0x30, 0x80);
>  		if (ret)
>  			return ret;

[PATCH net 2/3] net: dsa: lantiq_gswip: handle SPEED_2500 in gswip_port_set_speed()

[Jan Havran (Advantech Czech)]

The mxl-gsw1xx driver advertises 2500BASE-X on its SGMII port (via
supports_2500m and gsw1xx_phylink_get_caps()), but the shared
gswip_port_set_speed() has no SPEED_2500 case: at 2.5G every field keeps
its initializer, so mdio_phy = 0 pins the MDIO speed override to 10 Mbps
and no data passes.

At the MAC/MDIO level 2500BASE-X is identical to 1 Gbps (same wide GMII
datapath, same speed override); the rate itself is set in the PCS and
SerDes, not here. This matches the boot loader's PHY_ADDR_4 = 0x32A4 for
the 2.5G strap ("1 Gbps or above"), whose SPEED field is
GSWIP_MDIO_PHY_SPEED_G1 (the field has no encoding above G1). Share the
SPEED_1000 arm via a stacked case label. Its mii_cfg value is a no-op
for 2.5G: gswip_mii_mask_cfg() writes it only for the RGMII port
(mii_cfg[SGMII port] == -1), which cannot reach 2.5G anyway.

Fixes: 22335939ec90 ("net: dsa: add driver for MaxLinear GSW1xx switch family")
Signed-off-by: Jan Havran (Advantech Czech) <havran.jan@email.cz>
---
 drivers/net/dsa/lantiq/lantiq_gswip_common.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/dsa/lantiq/lantiq_gswip_common.c b/drivers/net/dsa/lantiq/lantiq_gswip_common.c
index 0e8eedf64d3a3..6150dc3ffb641 100644
--- a/drivers/net/dsa/lantiq/lantiq_gswip_common.c
+++ b/drivers/net/dsa/lantiq/lantiq_gswip_common.c
@@ -1339,6 +1339,7 @@ static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed,
 		break;
 
 	case SPEED_1000:
+	case SPEED_2500:
 		mdio_phy = GSWIP_MDIO_PHY_SPEED_G1;
 
 		mii_cfg = GSWIP_MII_CFG_RATE_M125;
-- 
2.39.5

Re: [PATCH net 2/3] net: dsa: lantiq_gswip: handle SPEED_2500 in gswip_port_set_speed()

[Maxime Chevallier]

Hi,

On 9/7/26 15:48, Jan Havran (Advantech Czech) wrote:
> The mxl-gsw1xx driver advertises 2500BASE-X on its SGMII port (via
> supports_2500m and gsw1xx_phylink_get_caps()), but the shared
> gswip_port_set_speed() has no SPEED_2500 case: at 2.5G every field keeps
> its initializer, so mdio_phy = 0 pins the MDIO speed override to 10 Mbps
> and no data passes.
> 
> At the MAC/MDIO level 2500BASE-X is identical to 1 Gbps (same wide GMII
> datapath, same speed override); the rate itself is set in the PCS and
> SerDes, not here. This matches the boot loader's PHY_ADDR_4 = 0x32A4 for
> the 2.5G strap ("1 Gbps or above"), whose SPEED field is
> GSWIP_MDIO_PHY_SPEED_G1 (the field has no encoding above G1). Share the
> SPEED_1000 arm via a stacked case label. Its mii_cfg value is a no-op
> for 2.5G: gswip_mii_mask_cfg() writes it only for the RGMII port
> (mii_cfg[SGMII port] == -1), which cannot reach 2.5G anyway.
> 
> Fixes: 22335939ec90 ("net: dsa: add driver for MaxLinear GSW1xx switch family")
> Signed-off-by: Jan Havran (Advantech Czech) <havran.jan@email.cz>

Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>

Maxime

> ---
>  drivers/net/dsa/lantiq/lantiq_gswip_common.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/net/dsa/lantiq/lantiq_gswip_common.c b/drivers/net/dsa/lantiq/lantiq_gswip_common.c
> index 0e8eedf64d3a3..6150dc3ffb641 100644
> --- a/drivers/net/dsa/lantiq/lantiq_gswip_common.c
> +++ b/drivers/net/dsa/lantiq/lantiq_gswip_common.c
> @@ -1339,6 +1339,7 @@ static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed,
>  		break;
>  
>  	case SPEED_1000:
> +	case SPEED_2500:
>  		mdio_phy = GSWIP_MDIO_PHY_SPEED_G1;
>  
>  		mii_cfg = GSWIP_MII_CFG_RATE_M125;

[PATCH net 3/3] net: dsa: lantiq_gswip: fix GSWIP_MDIO_PHY_FCONTX_EN value

[Jan Havran (Advantech Czech)]

Per the GSW145 data sheet, the FCONTX (bits 8:7) and FCONRX (bits 6:5)
flow-control fields of the PHY_ADDR_n register both encode 00 = AUTO,
01 = EN, 10 = reserved, 11 = DIS. GSWIP_MDIO_PHY_FCONTX_EN was 0x0100,
i.e. field value 10 (the reserved encoding), instead of 0x0080 (01 = EN);
FCONRX_EN is already 0x0020 (01). Enabling tx flow control therefore wrote
the reserved value.

Set FCONTX_EN to 0x0080. The register is shared by all supported parts.

Fixes: 14fceff4771e ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
Signed-off-by: Jan Havran (Advantech Czech) <havran.jan@email.cz>
---
 drivers/net/dsa/lantiq/lantiq_gswip.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.h b/drivers/net/dsa/lantiq/lantiq_gswip.h
index bc3686faad0d6..0b75be14dc109 100644
--- a/drivers/net/dsa/lantiq/lantiq_gswip.h
+++ b/drivers/net/dsa/lantiq/lantiq_gswip.h
@@ -42,7 +42,7 @@
 #define  GSWIP_MDIO_PHY_FDUP_DIS	0x0600
 #define  GSWIP_MDIO_PHY_FCONTX_MASK	0x0180
 #define  GSWIP_MDIO_PHY_FCONTX_AUTO	0x0000
-#define  GSWIP_MDIO_PHY_FCONTX_EN	0x0100
+#define  GSWIP_MDIO_PHY_FCONTX_EN	0x0080
 #define  GSWIP_MDIO_PHY_FCONTX_DIS	0x0180
 #define  GSWIP_MDIO_PHY_FCONRX_MASK	0x0060
 #define  GSWIP_MDIO_PHY_FCONRX_AUTO	0x0000
-- 
2.39.5

Re: [PATCH net 3/3] net: dsa: lantiq_gswip: fix GSWIP_MDIO_PHY_FCONTX_EN value

[Maxime Chevallier]

Hi,

On 9/7/26 15:48, Jan Havran (Advantech Czech) wrote:
> Per the GSW145 data sheet, the FCONTX (bits 8:7) and FCONRX (bits 6:5)
> flow-control fields of the PHY_ADDR_n register both encode 00 = AUTO,
> 01 = EN, 10 = reserved, 11 = DIS. GSWIP_MDIO_PHY_FCONTX_EN was 0x0100,
> i.e. field value 10 (the reserved encoding), instead of 0x0080 (01 = EN);
> FCONRX_EN is already 0x0020 (01). Enabling tx flow control therefore wrote
> the reserved value.
> 
> Set FCONTX_EN to 0x0080. The register is shared by all supported parts.
> 
> Fixes: 14fceff4771e ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
> Signed-off-by: Jan Havran (Advantech Czech) <havran.jan@email.cz>

Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>

Maxime

> ---
>  drivers/net/dsa/lantiq/lantiq_gswip.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.h b/drivers/net/dsa/lantiq/lantiq_gswip.h
> index bc3686faad0d6..0b75be14dc109 100644
> --- a/drivers/net/dsa/lantiq/lantiq_gswip.h
> +++ b/drivers/net/dsa/lantiq/lantiq_gswip.h
> @@ -42,7 +42,7 @@
>  #define  GSWIP_MDIO_PHY_FDUP_DIS	0x0600
>  #define  GSWIP_MDIO_PHY_FCONTX_MASK	0x0180
>  #define  GSWIP_MDIO_PHY_FCONTX_AUTO	0x0000
> -#define  GSWIP_MDIO_PHY_FCONTX_EN	0x0100
> +#define  GSWIP_MDIO_PHY_FCONTX_EN	0x0080
>  #define  GSWIP_MDIO_PHY_FCONTX_DIS	0x0180
>  #define  GSWIP_MDIO_PHY_FCONRX_MASK	0x0060
>  #define  GSWIP_MDIO_PHY_FCONRX_AUTO	0x0000

Re: [PATCH net 3/3] net: dsa: lantiq_gswip: fix GSWIP_MDIO_PHY_FCONTX_EN value

[Jakub Kicinski]

On Mon, 7 Sep 2026 18:28:32 +0200 Maxime Chevallier wrote:
> On 9/7/26 15:48, Jan Havran (Advantech Czech) wrote:
> > Per the GSW145 data sheet, the FCONTX (bits 8:7) and FCONRX (bits 6:5)
> > flow-control fields of the PHY_ADDR_n register both encode 00 = AUTO,
> > 01 = EN, 10 = reserved, 11 = DIS. GSWIP_MDIO_PHY_FCONTX_EN was 0x0100,
> > i.e. field value 10 (the reserved encoding), instead of 0x0080 (01 = EN);
> > FCONRX_EN is already 0x0020 (01). Enabling tx flow control therefore wrote
> > the reserved value.
> > 
> > Set FCONTX_EN to 0x0080. The register is shared by all supported parts.
> > 
> > Fixes: 14fceff4771e ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
> > Signed-off-by: Jan Havran (Advantech Czech) <havran.jan@email.cz>  
> 
> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>

Other than this last patch the series reads like net-next material 
to me TBH. New board enablement. Is that fair?

No need to repost either way.

And thanks for quick reviews!

Re: [PATCH net 3/3] net: dsa: lantiq_gswip: fix GSWIP_MDIO_PHY_FCONTX_EN value

[Jan Havran]

V Tue, Sep 08, 2026 at 05:43:22PM -0700, Jakub Kicinski napsal(a):
> On Mon, 7 Sep 2026 18:28:32 +0200 Maxime Chevallier wrote:
> > On 9/7/26 15:48, Jan Havran (Advantech Czech) wrote:
> > > Per the GSW145 data sheet, the FCONTX (bits 8:7) and FCONRX (bits 6:5)
> > > flow-control fields of the PHY_ADDR_n register both encode 00 = AUTO,
> > > 01 = EN, 10 = reserved, 11 = DIS. GSWIP_MDIO_PHY_FCONTX_EN was 0x0100,
> > > i.e. field value 10 (the reserved encoding), instead of 0x0080 (01 = EN);
> > > FCONRX_EN is already 0x0020 (01). Enabling tx flow control therefore wrote
> > > the reserved value.
> > > 
> > > Set FCONTX_EN to 0x0080. The register is shared by all supported parts.
> > > 
> > > Fixes: 14fceff4771e ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
> > > Signed-off-by: Jan Havran (Advantech Czech) <havran.jan@email.cz>  
> > 
> > Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
> 
> Other than this last patch the series reads like net-next material 
> to me TBH. New board enablement. Is that fair?
> 
> No need to repost either way.
> 
> And thanks for quick reviews!

Hi Jakub,
it makes sense to me. If there is no other board using different speed than the one
defined by the straps and also there is no other board running it at 2.5G speed,
then yes, it is new board enablement.

Sorry for the trouble. I had not thought about looking at it from this perspective.

Regards,
Jan

Re: [PATCH net 3/3] net: dsa: lantiq_gswip: fix GSWIP_MDIO_PHY_FCONTX_EN value

[Jakub Kicinski]

On Wed, 9 Sep 2026 22:43:11 +0200 Jan Havran wrote:
> V Tue, Sep 08, 2026 at 05:43:22PM -0700, Jakub Kicinski napsal(a):
> > Other than this last patch the series reads like net-next material 
> > to me TBH. New board enablement. Is that fair?
> > 
> > No need to repost either way.
> > 
> > And thanks for quick reviews!  
> 
> Hi Jakub,
> it makes sense to me. If there is no other board using different speed than the one
> defined by the straps and also there is no other board running it at 2.5G speed,
> then yes, it is new board enablement.
> 
> Sorry for the trouble. I had not thought about looking at it from this perspective.

No worries, thanks for a quick response!

Re: [PATCH net 0/3] net: dsa: lantiq_gswip: SGMII/2500BASE-X and flow-control fixes

[Daniel Golle]

On Mon, Sep 07, 2026 at 03:48:15PM +0200, Jan Havran (Advantech Czech) wrote:
> This series fixes three issues in the lantiq_gswip / mxl-gsw1xx DSA driver
> found while bringing up a MaxLinear GSW145 over SGMII on a Marvell
> Armada 7040 board, with the switch CPU port running 2500BASE-X and the
> user ports at 1000BASE-T.
> 
> Patch 1 reorders the SerDes NCO clock-rate setup ahead of the SGMII shell
> reset. Without it, only the rate the switch was left at by the straps or
> the boot loader links up; the other rate comes up but forwards no traffic.
> 
> Patch 2 adds the missing SPEED_2500 case to gswip_port_set_speed(); without
> it the CPU port was forced to 10 Mbps at 2.5G link-up.
> 
> Patch 3 corrects the GSWIP_MDIO_PHY_FCONTX_EN field value (a typo present
> since the original vrx200 driver).
> 
> Tested on GSW145 hardware only. The register values are backed by the
> public GSW145 data sheet and by the driver's own field encoding; the
> xRX200/xRX300 data sheets are not public.
> 
> Jan Havran (Advantech Czech) (3):
>   net: dsa: mxl-gsw1xx: set SerDes NCO rate before SGMII reset
>   net: dsa: lantiq_gswip: handle SPEED_2500 in gswip_port_set_speed()
>   net: dsa: lantiq_gswip: fix GSWIP_MDIO_PHY_FCONTX_EN value

Thank you for taking care of this on a board which allows you to actually
test it -- on the reference platform I had to develop the driver with the
SerDes interface of the switch is hard-wired to an MxL86111 PHY, hence I
could never test 2500Base-X mode.

Whole series
Reviewed-by: Daniel Golle <daniel@makrotopia.org>

Re: [PATCH net 0/3] net: dsa: lantiq_gswip: SGMII/2500BASE-X and flow-control fixes

[Jan Havran]

V Mon, Sep 07, 2026 at 06:22:48PM +0100, Daniel Golle napsal(a):
> On Mon, Sep 07, 2026 at 03:48:15PM +0200, Jan Havran (Advantech Czech) wrote:
> > This series fixes three issues in the lantiq_gswip / mxl-gsw1xx DSA driver
> > found while bringing up a MaxLinear GSW145 over SGMII on a Marvell
> > Armada 7040 board, with the switch CPU port running 2500BASE-X and the
> > user ports at 1000BASE-T.
> > 
> > Patch 1 reorders the SerDes NCO clock-rate setup ahead of the SGMII shell
> > reset. Without it, only the rate the switch was left at by the straps or
> > the boot loader links up; the other rate comes up but forwards no traffic.
> > 
> > Patch 2 adds the missing SPEED_2500 case to gswip_port_set_speed(); without
> > it the CPU port was forced to 10 Mbps at 2.5G link-up.
> > 
> > Patch 3 corrects the GSWIP_MDIO_PHY_FCONTX_EN field value (a typo present
> > since the original vrx200 driver).
> > 
> > Tested on GSW145 hardware only. The register values are backed by the
> > public GSW145 data sheet and by the driver's own field encoding; the
> > xRX200/xRX300 data sheets are not public.
> > 
> > Jan Havran (Advantech Czech) (3):
> >   net: dsa: mxl-gsw1xx: set SerDes NCO rate before SGMII reset
> >   net: dsa: lantiq_gswip: handle SPEED_2500 in gswip_port_set_speed()
> >   net: dsa: lantiq_gswip: fix GSWIP_MDIO_PHY_FCONTX_EN value
> 
> Thank you for taking care of this on a board which allows you to actually
> test it -- on the reference platform I had to develop the driver with the
> SerDes interface of the switch is hard-wired to an MxL86111 PHY, hence I
> could never test 2500Base-X mode.
> 
> Whole series
> Reviewed-by: Daniel Golle <daniel@makrotopia.org>

Thank you, Daniel.
We are developing a new board containing this switch and we found your upstream driver
in a much better shape than the official Maxlinear driver.

Unfortunatelly 2.5G did not work for us because of the missing SPEED_2500 case and
1G did not work because the switch was left in 2.5G mode by the straps.

But with these fixes, this driver works great for us.

Thanks again for your work on this driver.
Regards,
Jan

Re: [PATCH net 0/3] net: dsa: lantiq_gswip: SGMII/2500BASE-X and flow-control fixes

[patchwork-bot+netdevbpf]

Hello:

This series was applied to netdev/net.git (main)
by Jakub Kicinski <kuba@kernel.org>:

On Mon,  7 Sep 2026 15:48:15 +0200 you wrote:
> This series fixes three issues in the lantiq_gswip / mxl-gsw1xx DSA driver
> found while bringing up a MaxLinear GSW145 over SGMII on a Marvell
> Armada 7040 board, with the switch CPU port running 2500BASE-X and the
> user ports at 1000BASE-T.
> 
> Patch 1 reorders the SerDes NCO clock-rate setup ahead of the SGMII shell
> reset. Without it, only the rate the switch was left at by the straps or
> the boot loader links up; the other rate comes up but forwards no traffic.
> 
> [...]

Here is the summary with links:
  - [net,1/3] net: dsa: mxl-gsw1xx: set SerDes NCO rate before SGMII reset
    (no matching commit)
  - [net,2/3] net: dsa: lantiq_gswip: handle SPEED_2500 in gswip_port_set_speed()
    (no matching commit)
  - [net,3/3] net: dsa: lantiq_gswip: fix GSWIP_MDIO_PHY_FCONTX_EN value
    https://git.kernel.org/netdev/net/c/59fb389ad6bf

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html

Re: [PATCH net 0/3] net: dsa: lantiq_gswip: SGMII/2500BASE-X and flow-control fixes

[patchwork-bot+netdevbpf]

Hello:

This series was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba@kernel.org>:

On Mon,  7 Sep 2026 15:48:15 +0200 you wrote:
> This series fixes three issues in the lantiq_gswip / mxl-gsw1xx DSA driver
> found while bringing up a MaxLinear GSW145 over SGMII on a Marvell
> Armada 7040 board, with the switch CPU port running 2500BASE-X and the
> user ports at 1000BASE-T.
> 
> Patch 1 reorders the SerDes NCO clock-rate setup ahead of the SGMII shell
> reset. Without it, only the rate the switch was left at by the straps or
> the boot loader links up; the other rate comes up but forwards no traffic.
> 
> [...]

Here is the summary with links:
  - [net,1/3] net: dsa: mxl-gsw1xx: set SerDes NCO rate before SGMII reset
    https://git.kernel.org/netdev/net-next/c/40c578ceaeec
  - [net,2/3] net: dsa: lantiq_gswip: handle SPEED_2500 in gswip_port_set_speed()
    https://git.kernel.org/netdev/net-next/c/6b597ba4c2f6
  - [net,3/3] net: dsa: lantiq_gswip: fix GSWIP_MDIO_PHY_FCONTX_EN value
    (no matching commit)

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html