Re: [PATCHSET] block: fix PIO cache coherency bug

[Russell King <rmk+lkml@arm.linux.org.uk>]

On Thu, Mar 02, 2006 at 12:46:28PM -0600, James Bottomley wrote:
> On Wed, 2006-02-22 at 17:27 +0900, Tejun Heo wrote:
> > The objection raised by James Bottomley is that although syncing the
> > kernel page is the responsbility of the driver, syncing user page is
> > not; thus, use of flush_dcache_page() is excessive.  James suggested
> > use of flush_kernel_dcache_page().
> 
> The problem is that it's not only excessive, it would entangle us with
> mm locking.  Basically, all you want to ensure is that the underlying
> memory has the information after you've done (rather than the CPU
> cache), flush_kernel_dcache_page() will achieve this.  The block layer
> itself takes care of user space coherency.

Your understanding of the problem on ARM remains fundamentally flawed.
I see no way to resolve this since you don't seem to listen or accept
my reasoning.

Therefore, message I'm getting from you is that we are not allowed to
have an ARM system which can possibly work correctly with PIO.

As a result, I have no further interest in trying to resolve this issue,
period.  ARM people will just have to accept that PIO mode IDE drivers
just will not be an option.

Thanks.

-- 
Russell King
 Linux kernel    2.6 ARM Linux   - http://www.arm.linux.org.uk/
 maintainer of:  2.6 Serial core