Re: [PATCH 18/18] 2.6.17.9 perfmon2 patch for review: new x86_64 files

[Stephane Eranian <eranian@hpl.hp.com>]

Andi,

On Wed, Aug 23, 2006 at 01:22:44PM +0200, Andi Kleen wrote:
> 
> > I have a second thought on this. AMD has architected the performance counters.
> 
> Quote:
> >>
> Implementations are not required to support the performance
> c o u n t e rs and the event-select registers, or the time-stamp
> counter. The presence of these features can be determined by
> <<
> 
At the end of this paragraph then mention using CPUID to determine
the presence of the counters. AFAIK, there is no feature bit
covering performance monitoring. Does that mean we are left
with having to check the family and model number just like on
Intel?


> Also all code I've seen checked the family at least.
> 
> 
> > Their specification is not part of a model specific documentation but
> > part of the AMD64 architecure. 
> 
> The high level specification is, but not the actual counters for once.
> 
> > What I don't not quite understand with the K7, K8 terminology is the
> > relation/dependencies with the AMD64 architecture specification.
> AMD64 gives a high level register format, K7/K8 is the actual list 
> of performance counters.

Ok, I think I understand now:
	1/ Bios and Kernel Developer Guide from Ahtlon64 and Opteron 64 is
	  what you are talking about with K7/K8
	2/ AMD64 Architecture Programmer's Manual is the generic AMD64 description

So in theory, we should have:
	- a generic PMU description for the architected PMU  as described in 2/
	- a K7/K8 PMU description table for Athlon64 and Opteron64 as described in 1/

AFAIK, K7/K8 do not add anything to the architected PMU. I'll rename what we have to perfmon_k8.c
to make it more explicit.

-- 
-Stephane