From: Stephane Eranian <eranian@hpl.hp.com>
To: Andi Kleen <ak@suse.de>
Cc: linux-kernel@vger.kernel.org, discuss@x86-64.org
Subject: Re: [PATCH 18/18] 2.6.17.9 perfmon2 patch for review: new x86_64 files
Date: Wed, 23 Aug 2006 06:48:15 -0700 [thread overview]
Message-ID: <20060823134815.GH697@frankl.hpl.hp.com> (raw)
In-Reply-To: <200608231544.26756.ak@suse.de>
Andi,
On Wed, Aug 23, 2006 at 03:44:26PM +0200, Andi Kleen wrote:
> > If they have variations it could be with
> > the low power (laptop) models where counters may not be present at all.
>
> It would surprise me if they ever released anything again with no counters.
>
> It's mainly simulators where the counters are missing (e.g. SimNow is a pretty
> accurate simulation otherwise, but doesn't have performance counters)
>
Ah yes simulators are a good example. Yet what matters is whether or not they
would fault on access to the MSR. It is okay if they implement the MSR but
they do not count anything, nor trigger interrupts. The IA-64 ski simulator is
like this and this is just fine, all you get is zeroes and you cannot sample.
--
-Stephane
prev parent reply other threads:[~2006-08-23 13:58 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-08-23 8:06 Stephane Eranian
2006-08-23 10:19 ` Andi Kleen
2006-08-23 10:29 ` Stephane Eranian
2006-08-23 15:25 ` Christoph Hellwig
2006-08-23 15:53 ` Stephane Eranian
2006-08-23 20:57 ` Christoph Hellwig
2006-08-23 10:39 ` Stephane Eranian
2006-08-23 11:22 ` Andi Kleen
2006-08-23 12:14 ` Stephane Eranian
2006-08-23 12:29 ` Andi Kleen
2006-08-23 12:58 ` Stephane Eranian
2006-08-23 13:44 ` Andi Kleen
2006-08-23 13:48 ` Stephane Eranian [this message]
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