* [PATCH] calgary: Increase the maximum PHB bus number
@ 2009-12-09 0:59 Darrick J. Wong
2009-12-09 5:04 ` Jon Mason
[not found] ` <20091209090346.GN2452@tyrion.haifa.ibm.com>
0 siblings, 2 replies; 8+ messages in thread
From: Darrick J. Wong @ 2009-12-09 0:59 UTC (permalink / raw)
To: Ingo Molnar
Cc: Jon D. Mason, discuss, Corinna Schultz, Muli Ben-Yehuda, linux-kernel
Newer systems (x3950M2) can have 48 PHBs per chassis and 8 chassis, so bump the
limits up and provide an explanation of the requirements for each class.
Signed-off-by: Darrick J. Wong <djwong@us.ibm.com>
---
arch/x86/kernel/pci-calgary_64.c | 13 +++++++++----
1 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
index e6ec8a2..a693037 100644
--- a/arch/x86/kernel/pci-calgary_64.c
+++ b/arch/x86/kernel/pci-calgary_64.c
@@ -102,10 +102,15 @@ int use_calgary __read_mostly = 0;
#define PMR_SOFTSTOPFAULT 0x40000000
#define PMR_HARDSTOP 0x20000000
-#define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
-#define MAX_NUM_CHASSIS 8 /* max number of chassis */
-/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
-#define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
+/*
+ The maximum PHB bus number.
+ x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
+ x3950M2: 4 chassis, 48 PHBs per chassis = 192
+ x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
+ x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
+*/
+#define MAX_PHB_BUS_NUM 384
+
#define PHBS_PER_CALGARY 4
/* register offsets in Calgary's internal register space */
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] calgary: Increase the maximum PHB bus number
2009-12-09 0:59 [PATCH] calgary: Increase the maximum PHB bus number Darrick J. Wong
@ 2009-12-09 5:04 ` Jon Mason
2009-12-09 18:40 ` [PATCH v2] " Darrick J. Wong
[not found] ` <20091209090346.GN2452@tyrion.haifa.ibm.com>
1 sibling, 1 reply; 8+ messages in thread
From: Jon Mason @ 2009-12-09 5:04 UTC (permalink / raw)
To: djwong
Cc: Ingo Molnar, discuss, Corinna Schultz, Muli Ben-Yehuda, linux-kernel
It looks fine, but please change the comment to be similar to the
other multi-line comments in the code. This would look like:
/*
* The maximum PHB bus number.
* x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
* x3950M2: 4 chassis, 48 PHBs per chassis = 192
* x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
* x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
*/
Thanks,
Jon
On Tue, Dec 8, 2009 at 6:59 PM, Darrick J. Wong <djwong@us.ibm.com> wrote:
> Newer systems (x3950M2) can have 48 PHBs per chassis and 8 chassis, so bump the
> limits up and provide an explanation of the requirements for each class.
>
> Signed-off-by: Darrick J. Wong <djwong@us.ibm.com>
> ---
>
> arch/x86/kernel/pci-calgary_64.c | 13 +++++++++----
> 1 files changed, 9 insertions(+), 4 deletions(-)
>
>
> diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
> index e6ec8a2..a693037 100644
> --- a/arch/x86/kernel/pci-calgary_64.c
> +++ b/arch/x86/kernel/pci-calgary_64.c
> @@ -102,10 +102,15 @@ int use_calgary __read_mostly = 0;
> #define PMR_SOFTSTOPFAULT 0x40000000
> #define PMR_HARDSTOP 0x20000000
>
> -#define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
> -#define MAX_NUM_CHASSIS 8 /* max number of chassis */
> -/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
> -#define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
> +/*
> + The maximum PHB bus number.
> + x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
> + x3950M2: 4 chassis, 48 PHBs per chassis = 192
> + x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
> + x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
> +*/
> +#define MAX_PHB_BUS_NUM 384
> +
> #define PHBS_PER_CALGARY 4
>
> /* register offsets in Calgary's internal register space */
>
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v2] calgary: Increase the maximum PHB bus number
2009-12-09 5:04 ` Jon Mason
@ 2009-12-09 18:40 ` Darrick J. Wong
2009-12-09 19:37 ` Jon Mason
0 siblings, 1 reply; 8+ messages in thread
From: Darrick J. Wong @ 2009-12-09 18:40 UTC (permalink / raw)
To: Jon Mason
Cc: Ingo Molnar, discuss, Corinna Schultz, Muli Ben-Yehuda, linux-kernel
Newer systems (x3950M2) can have 48 PHBs per chassis and 8 chassis, so bump the
limits up and provide an explanation of the requirements for each class.
Signed-off-by: Darrick J. Wong <djwong@us.ibm.com>
Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
---
arch/x86/kernel/pci-calgary_64.c | 13 +++++++++----
1 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
index e6ec8a2..4b7eb90 100644
--- a/arch/x86/kernel/pci-calgary_64.c
+++ b/arch/x86/kernel/pci-calgary_64.c
@@ -102,10 +102,15 @@ int use_calgary __read_mostly = 0;
#define PMR_SOFTSTOPFAULT 0x40000000
#define PMR_HARDSTOP 0x20000000
-#define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
-#define MAX_NUM_CHASSIS 8 /* max number of chassis */
-/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
-#define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
+/*
+ * The maximum PHB bus number.
+ * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
+ * x3950M2: 4 chassis, 48 PHBs per chassis = 192
+ * x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
+ * x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
+ */
+#define MAX_PHB_BUS_NUM 384
+
#define PHBS_PER_CALGARY 4
/* register offsets in Calgary's internal register space */
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2] calgary: Increase the maximum PHB bus number
2009-12-09 18:40 ` [PATCH v2] " Darrick J. Wong
@ 2009-12-09 19:37 ` Jon Mason
0 siblings, 0 replies; 8+ messages in thread
From: Jon Mason @ 2009-12-09 19:37 UTC (permalink / raw)
To: djwong
Cc: Ingo Molnar, discuss, Corinna Schultz, Muli Ben-Yehuda, linux-kernel
Thanks for fixing the comment
Acked-by: Jon Mason <jdmason@kudzu.us>
On Wed, Dec 9, 2009 at 12:40 PM, Darrick J. Wong <djwong@us.ibm.com> wrote:
> Newer systems (x3950M2) can have 48 PHBs per chassis and 8 chassis, so bump the
> limits up and provide an explanation of the requirements for each class.
>
> Signed-off-by: Darrick J. Wong <djwong@us.ibm.com>
> Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
> ---
>
> arch/x86/kernel/pci-calgary_64.c | 13 +++++++++----
> 1 files changed, 9 insertions(+), 4 deletions(-)
>
>
> diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
> index e6ec8a2..4b7eb90 100644
> --- a/arch/x86/kernel/pci-calgary_64.c
> +++ b/arch/x86/kernel/pci-calgary_64.c
> @@ -102,10 +102,15 @@ int use_calgary __read_mostly = 0;
> #define PMR_SOFTSTOPFAULT 0x40000000
> #define PMR_HARDSTOP 0x20000000
>
> -#define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
> -#define MAX_NUM_CHASSIS 8 /* max number of chassis */
> -/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
> -#define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
> +/*
> + * The maximum PHB bus number.
> + * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
> + * x3950M2: 4 chassis, 48 PHBs per chassis = 192
> + * x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
> + * x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
> + */
> +#define MAX_PHB_BUS_NUM 384
> +
> #define PHBS_PER_CALGARY 4
>
> /* register offsets in Calgary's internal register space */
>
^ permalink raw reply [flat|nested] 8+ messages in thread
[parent not found: <20091209090346.GN2452@tyrion.haifa.ibm.com>]
* Re: [PATCH] calgary: Increase the maximum PHB bus number
[not found] ` <20091209090346.GN2452@tyrion.haifa.ibm.com>
@ 2010-02-18 18:37 ` Darrick J. Wong
2010-02-20 7:18 ` Muli Ben-Yehuda
0 siblings, 1 reply; 8+ messages in thread
From: Darrick J. Wong @ 2010-02-18 18:37 UTC (permalink / raw)
To: Muli Ben-Yehuda
Cc: Ingo Molnar, Jon D. Mason, discuss, Corinna Schultz, linux-kernel
On Wed, Dec 09, 2009 at 11:03:46AM +0200, Muli Ben-Yehuda wrote:
> On Tue, Dec 08, 2009 at 04:59:01PM -0800, Darrick J. Wong wrote:
>
> > -#define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
> > -#define MAX_NUM_CHASSIS 8 /* max number of chassis */
> > -/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
> > -#define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
> > +/*
> > + The maximum PHB bus number.
> > + x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
> > + x3950M2: 4 chassis, 48 PHBs per chassis = 192
> > + x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
> > + x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
> > +*/
> > +#define MAX_PHB_BUS_NUM 384
> > +
> > #define PHBS_PER_CALGARY 4
>
> We'll end up wasting a few bytes on small systems, but I don't think
> it's enough to matter on these fairly large systems. As far as I'm
> concerned, patch is fine.
>
> Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
Hmm... has this patch been queued up by anyone for the .34 merge window?
--D
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] calgary: Increase the maximum PHB bus number
2010-02-18 18:37 ` [PATCH] " Darrick J. Wong
@ 2010-02-20 7:18 ` Muli Ben-Yehuda
2010-04-06 18:09 ` Darrick J. Wong
0 siblings, 1 reply; 8+ messages in thread
From: Muli Ben-Yehuda @ 2010-02-20 7:18 UTC (permalink / raw)
To: Darrick J. Wong
Cc: Ingo Molnar, Jon D. Mason, discuss, Corinna Schultz, linux-kernel
On Thu, Feb 18, 2010 at 10:37:50AM -0800, Darrick J. Wong wrote:
> On Wed, Dec 09, 2009 at 11:03:46AM +0200, Muli Ben-Yehuda wrote:
> > On Tue, Dec 08, 2009 at 04:59:01PM -0800, Darrick J. Wong wrote:
> >
> > > -#define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
> > > -#define MAX_NUM_CHASSIS 8 /* max number of chassis */
> > > -/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
> > > -#define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
> > > +/*
> > > + The maximum PHB bus number.
> > > + x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
> > > + x3950M2: 4 chassis, 48 PHBs per chassis = 192
> > > + x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
> > > + x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
> > > +*/
> > > +#define MAX_PHB_BUS_NUM 384
> > > +
> > > #define PHBS_PER_CALGARY 4
> >
> > We'll end up wasting a few bytes on small systems, but I don't think
> > it's enough to matter on these fairly large systems. As far as I'm
> > concerned, patch is fine.
> >
> > Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
>
> Hmm... has this patch been queued up by anyone for the .34 merge
> window?
I don't maintain a separate Calgary patchset anymore, hopefully Ingo
or one of the other x86 maintainers have picked it up?
Cheers,
Muli
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] calgary: Increase the maximum PHB bus number
2010-02-20 7:18 ` Muli Ben-Yehuda
@ 2010-04-06 18:09 ` Darrick J. Wong
0 siblings, 0 replies; 8+ messages in thread
From: Darrick J. Wong @ 2010-04-06 18:09 UTC (permalink / raw)
To: Muli Ben-Yehuda
Cc: Ingo Molnar, Jon D. Mason, discuss, Corinna Schultz, linux-kernel
On Sat, Feb 20, 2010 at 09:18:05AM +0200, Muli Ben-Yehuda wrote:
> On Thu, Feb 18, 2010 at 10:37:50AM -0800, Darrick J. Wong wrote:
> > On Wed, Dec 09, 2009 at 11:03:46AM +0200, Muli Ben-Yehuda wrote:
> > > On Tue, Dec 08, 2009 at 04:59:01PM -0800, Darrick J. Wong wrote:
> > >
> > > > -#define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
> > > > -#define MAX_NUM_CHASSIS 8 /* max number of chassis */
> > > > -/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
> > > > -#define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
> > > > +/*
> > > > + The maximum PHB bus number.
> > > > + x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
> > > > + x3950M2: 4 chassis, 48 PHBs per chassis = 192
> > > > + x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
> > > > + x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
> > > > +*/
> > > > +#define MAX_PHB_BUS_NUM 384
> > > > +
> > > > #define PHBS_PER_CALGARY 4
> > >
> > > We'll end up wasting a few bytes on small systems, but I don't think
> > > it's enough to matter on these fairly large systems. As far as I'm
> > > concerned, patch is fine.
> > >
> > > Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
> >
> > Hmm... has this patch been queued up by anyone for the .34 merge
> > window?
>
> I don't maintain a separate Calgary patchset anymore, hopefully Ingo
> or one of the other x86 maintainers have picked it up?
Still not in 2.6.34-rc3. Are there any objections to this patch? I've not
heard any complaints since my original posting... or did it simply get lost in
the noise?
--D
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] calgary: Increase the maximum PHB bus number
@ 2010-05-24 23:52 Corinna Schultz
0 siblings, 0 replies; 8+ messages in thread
From: Corinna Schultz @ 2010-05-24 23:52 UTC (permalink / raw)
To: linux-kernel; +Cc: mingo, djwong
On Apr 06, 2010, Darrick J. Wong wrote:
> On Thu, Feb 18, 2010 at 10:37:50AM -0800, Darrick J. Wong wrote:
> > On Wed, Dec 09, 2009 at 11:03:46AM +0200, Muli Ben-Yehuda wrote:
> > > On Tue, Dec 08, 2009 at 04:59:01PM -0800, Darrick J. Wong wrote:
> > > > > > -#define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
> > > > -#define MAX_NUM_CHASSIS 8 /* max number of chassis */
> > > > -/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
> > > > -#define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
> > > > +/*
> > > > + The maximum PHB bus number.
> > > > + x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
> > > > + x3950M2: 4 chassis, 48 PHBs per chassis = 192
> > > > + x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
> > > > + x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
> > > > +*/
> > > > +#define MAX_PHB_BUS_NUM 384
> > > > +
> > > > #define PHBS_PER_CALGARY 4
> > > > > We'll end up wasting a few bytes on small systems, but I don't think
> > > it's enough to matter on these fairly large systems. As far as I'm
> > > concerned, patch is fine.
> > > > > Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
> > > Hmm... has this patch been queued up by anyone for the .34 merge
> > window?
> Still not in 2.6.34-rc3. Are there any objections to this patch? I've not
> heard any complaints since my original posting... or did it simply
> get lost in
> the noise?
This patch still hasn't been picked up by a maintainer.
Are there any objections?
-Corinna Schultz
IBM LTC
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2010-05-24 23:52 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2009-12-09 0:59 [PATCH] calgary: Increase the maximum PHB bus number Darrick J. Wong
2009-12-09 5:04 ` Jon Mason
2009-12-09 18:40 ` [PATCH v2] " Darrick J. Wong
2009-12-09 19:37 ` Jon Mason
[not found] ` <20091209090346.GN2452@tyrion.haifa.ibm.com>
2010-02-18 18:37 ` [PATCH] " Darrick J. Wong
2010-02-20 7:18 ` Muli Ben-Yehuda
2010-04-06 18:09 ` Darrick J. Wong
2010-05-24 23:52 Corinna Schultz
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