[PATCH] calgary: Increase the maximum PHB bus number

[PATCH] calgary: Increase the maximum PHB bus number

[Darrick J. Wong]

Newer systems (x3950M2) can have 48 PHBs per chassis and 8 chassis, so bump the
limits up and provide an explanation of the requirements for each class.

Signed-off-by: Darrick J. Wong <djwong@us.ibm.com>
---

 arch/x86/kernel/pci-calgary_64.c |   13 +++++++++----
 1 files changed, 9 insertions(+), 4 deletions(-)


diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
index e6ec8a2..a693037 100644
--- a/arch/x86/kernel/pci-calgary_64.c
+++ b/arch/x86/kernel/pci-calgary_64.c
@@ -102,10 +102,15 @@ int use_calgary __read_mostly = 0;
 #define PMR_SOFTSTOPFAULT	0x40000000
 #define PMR_HARDSTOP		0x20000000
 
-#define MAX_NUM_OF_PHBS		8 /* how many PHBs in total? */
-#define MAX_NUM_CHASSIS		8 /* max number of chassis */
-/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
-#define MAX_PHB_BUS_NUM		(MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
+/*
+   The maximum PHB bus number.
+   x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
+   x3950M2: 4 chassis, 48 PHBs per chassis        = 192
+   x3950 (PCIE): 8 chassis, 32 PHBs per chassis   = 256
+   x3950 (PCIX): 8 chassis, 16 PHBs per chassis   = 128
+*/
+#define MAX_PHB_BUS_NUM		384
+
 #define PHBS_PER_CALGARY	4
 
 /* register offsets in Calgary's internal register space */

Re: [PATCH] calgary: Increase the maximum PHB bus number

[Jon Mason]

It looks fine, but please change the comment to be similar to the
other multi-line comments in the code.  This would look like:

/*
 * The maximum PHB bus number.
 * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
 * x3950M2: 4 chassis, 48 PHBs per chassis           = 192
 * x3950 (PCIE): 8 chassis, 32 PHBs per chassis     = 256
 * x3950 (PCIX): 8 chassis, 16 PHBs per chassis     = 128
 */

Thanks,
Jon

On Tue, Dec 8, 2009 at 6:59 PM, Darrick J. Wong <djwong@us.ibm.com> wrote:
> Newer systems (x3950M2) can have 48 PHBs per chassis and 8 chassis, so bump the
> limits up and provide an explanation of the requirements for each class.
>
> Signed-off-by: Darrick J. Wong <djwong@us.ibm.com>
> ---
>
>  arch/x86/kernel/pci-calgary_64.c |   13 +++++++++----
>  1 files changed, 9 insertions(+), 4 deletions(-)
>
>
> diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
> index e6ec8a2..a693037 100644
> --- a/arch/x86/kernel/pci-calgary_64.c
> +++ b/arch/x86/kernel/pci-calgary_64.c
> @@ -102,10 +102,15 @@ int use_calgary __read_mostly = 0;
>  #define PMR_SOFTSTOPFAULT      0x40000000
>  #define PMR_HARDSTOP           0x20000000
>
> -#define MAX_NUM_OF_PHBS                8 /* how many PHBs in total? */
> -#define MAX_NUM_CHASSIS                8 /* max number of chassis */
> -/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
> -#define MAX_PHB_BUS_NUM                (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
> +/*
> +   The maximum PHB bus number.
> +   x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
> +   x3950M2: 4 chassis, 48 PHBs per chassis        = 192
> +   x3950 (PCIE): 8 chassis, 32 PHBs per chassis   = 256
> +   x3950 (PCIX): 8 chassis, 16 PHBs per chassis   = 128
> +*/
> +#define MAX_PHB_BUS_NUM                384
> +
>  #define PHBS_PER_CALGARY       4
>
>  /* register offsets in Calgary's internal register space */
>

[PATCH v2] calgary: Increase the maximum PHB bus number

[Darrick J. Wong]

Newer systems (x3950M2) can have 48 PHBs per chassis and 8 chassis, so bump the
limits up and provide an explanation of the requirements for each class.

Signed-off-by: Darrick J. Wong <djwong@us.ibm.com>
Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
---

 arch/x86/kernel/pci-calgary_64.c |   13 +++++++++----
 1 files changed, 9 insertions(+), 4 deletions(-)


diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
index e6ec8a2..4b7eb90 100644
--- a/arch/x86/kernel/pci-calgary_64.c
+++ b/arch/x86/kernel/pci-calgary_64.c
@@ -102,10 +102,15 @@ int use_calgary __read_mostly = 0;
 #define PMR_SOFTSTOPFAULT	0x40000000
 #define PMR_HARDSTOP		0x20000000
 
-#define MAX_NUM_OF_PHBS		8 /* how many PHBs in total? */
-#define MAX_NUM_CHASSIS		8 /* max number of chassis */
-/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
-#define MAX_PHB_BUS_NUM		(MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
+/*
+ * The maximum PHB bus number.
+ * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
+ * x3950M2: 4 chassis, 48 PHBs per chassis        = 192
+ * x3950 (PCIE): 8 chassis, 32 PHBs per chassis   = 256
+ * x3950 (PCIX): 8 chassis, 16 PHBs per chassis   = 128
+ */
+#define MAX_PHB_BUS_NUM		384
+
 #define PHBS_PER_CALGARY	4
 
 /* register offsets in Calgary's internal register space */

Re: [PATCH v2] calgary: Increase the maximum PHB bus number

[Jon Mason]

Thanks for fixing the comment

Acked-by: Jon Mason <jdmason@kudzu.us>

On Wed, Dec 9, 2009 at 12:40 PM, Darrick J. Wong <djwong@us.ibm.com> wrote:
> Newer systems (x3950M2) can have 48 PHBs per chassis and 8 chassis, so bump the
> limits up and provide an explanation of the requirements for each class.
>
> Signed-off-by: Darrick J. Wong <djwong@us.ibm.com>
> Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
> ---
>
>  arch/x86/kernel/pci-calgary_64.c |   13 +++++++++----
>  1 files changed, 9 insertions(+), 4 deletions(-)
>
>
> diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
> index e6ec8a2..4b7eb90 100644
> --- a/arch/x86/kernel/pci-calgary_64.c
> +++ b/arch/x86/kernel/pci-calgary_64.c
> @@ -102,10 +102,15 @@ int use_calgary __read_mostly = 0;
>  #define PMR_SOFTSTOPFAULT      0x40000000
>  #define PMR_HARDSTOP           0x20000000
>
> -#define MAX_NUM_OF_PHBS                8 /* how many PHBs in total? */
> -#define MAX_NUM_CHASSIS                8 /* max number of chassis */
> -/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
> -#define MAX_PHB_BUS_NUM                (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
> +/*
> + * The maximum PHB bus number.
> + * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
> + * x3950M2: 4 chassis, 48 PHBs per chassis        = 192
> + * x3950 (PCIE): 8 chassis, 32 PHBs per chassis   = 256
> + * x3950 (PCIX): 8 chassis, 16 PHBs per chassis   = 128
> + */
> +#define MAX_PHB_BUS_NUM                384
> +
>  #define PHBS_PER_CALGARY       4
>
>  /* register offsets in Calgary's internal register space */
>

Re: [PATCH] calgary: Increase the maximum PHB bus number

[Darrick J. Wong]

On Wed, Dec 09, 2009 at 11:03:46AM +0200, Muli Ben-Yehuda wrote:
> On Tue, Dec 08, 2009 at 04:59:01PM -0800, Darrick J. Wong wrote:
> 
> > -#define MAX_NUM_OF_PHBS		8 /* how many PHBs in total? */
> > -#define MAX_NUM_CHASSIS		8 /* max number of chassis */
> > -/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
> > -#define MAX_PHB_BUS_NUM		(MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
> > +/*
> > +   The maximum PHB bus number.
> > +   x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
> > +   x3950M2: 4 chassis, 48 PHBs per chassis        = 192
> > +   x3950 (PCIE): 8 chassis, 32 PHBs per chassis   = 256
> > +   x3950 (PCIX): 8 chassis, 16 PHBs per chassis   = 128
> > +*/
> > +#define MAX_PHB_BUS_NUM		384
> > +
> >  #define PHBS_PER_CALGARY	4
> 
> We'll end up wasting a few bytes on small systems, but I don't think
> it's enough to matter on these fairly large systems. As far as I'm
> concerned, patch is fine.
> 
> Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>

Hmm... has this patch been queued up by anyone for the .34 merge window?

--D

Re: [PATCH] calgary: Increase the maximum PHB bus number

[Muli Ben-Yehuda]

On Thu, Feb 18, 2010 at 10:37:50AM -0800, Darrick J. Wong wrote:
> On Wed, Dec 09, 2009 at 11:03:46AM +0200, Muli Ben-Yehuda wrote:
> > On Tue, Dec 08, 2009 at 04:59:01PM -0800, Darrick J. Wong wrote:
> > 
> > > -#define MAX_NUM_OF_PHBS		8 /* how many PHBs in total? */
> > > -#define MAX_NUM_CHASSIS		8 /* max number of chassis */
> > > -/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
> > > -#define MAX_PHB_BUS_NUM		(MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
> > > +/*
> > > +   The maximum PHB bus number.
> > > +   x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
> > > +   x3950M2: 4 chassis, 48 PHBs per chassis        = 192
> > > +   x3950 (PCIE): 8 chassis, 32 PHBs per chassis   = 256
> > > +   x3950 (PCIX): 8 chassis, 16 PHBs per chassis   = 128
> > > +*/
> > > +#define MAX_PHB_BUS_NUM		384
> > > +
> > >  #define PHBS_PER_CALGARY	4
> > 
> > We'll end up wasting a few bytes on small systems, but I don't think
> > it's enough to matter on these fairly large systems. As far as I'm
> > concerned, patch is fine.
> > 
> > Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
> 
> Hmm... has this patch been queued up by anyone for the .34 merge
> window?

I don't maintain a separate Calgary patchset anymore, hopefully Ingo
or one of the other x86 maintainers have picked it up?

Cheers,
Muli

Re: [PATCH] calgary: Increase the maximum PHB bus number

[Darrick J. Wong]

On Sat, Feb 20, 2010 at 09:18:05AM +0200, Muli Ben-Yehuda wrote:
> On Thu, Feb 18, 2010 at 10:37:50AM -0800, Darrick J. Wong wrote:
> > On Wed, Dec 09, 2009 at 11:03:46AM +0200, Muli Ben-Yehuda wrote:
> > > On Tue, Dec 08, 2009 at 04:59:01PM -0800, Darrick J. Wong wrote:
> > > 
> > > > -#define MAX_NUM_OF_PHBS		8 /* how many PHBs in total? */
> > > > -#define MAX_NUM_CHASSIS		8 /* max number of chassis */
> > > > -/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
> > > > -#define MAX_PHB_BUS_NUM		(MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
> > > > +/*
> > > > +   The maximum PHB bus number.
> > > > +   x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
> > > > +   x3950M2: 4 chassis, 48 PHBs per chassis        = 192
> > > > +   x3950 (PCIE): 8 chassis, 32 PHBs per chassis   = 256
> > > > +   x3950 (PCIX): 8 chassis, 16 PHBs per chassis   = 128
> > > > +*/
> > > > +#define MAX_PHB_BUS_NUM		384
> > > > +
> > > >  #define PHBS_PER_CALGARY	4
> > > 
> > > We'll end up wasting a few bytes on small systems, but I don't think
> > > it's enough to matter on these fairly large systems. As far as I'm
> > > concerned, patch is fine.
> > > 
> > > Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
> > 
> > Hmm... has this patch been queued up by anyone for the .34 merge
> > window?
> 
> I don't maintain a separate Calgary patchset anymore, hopefully Ingo
> or one of the other x86 maintainers have picked it up?

Still not in 2.6.34-rc3.  Are there any objections to this patch?  I've not
heard any complaints since my original posting... or did it simply get lost in
the noise?

--D