From: Jiri Olsa <jolsa@redhat.com>
To: Stephane Eranian <eranian@google.com>
Cc: LKML <linux-kernel@vger.kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
"mingo@elte.hu" <mingo@elte.hu>,
"ak@linux.intel.com" <ak@linux.intel.com>,
"Liang, Kan" <kan.liang@intel.com>,
Borislav Petkov <bp@alien8.de>,
Maria Dimakopoulou <maria.n.dimakopoulou@gmail.com>
Subject: Re: [PATCH v2 06/12] perf/x86: implement cross-HT corruption bug workaround
Date: Thu, 23 Oct 2014 10:13:12 +0200 [thread overview]
Message-ID: <20141023081312.GA7166@krava.brq.redhat.com> (raw)
In-Reply-To: <CABPqkBT7y0CjozJ9VtkK6KrTGEwYaTzX+Qt6UD-Y9jHXNzu86g@mail.gmail.com>
On Thu, Oct 23, 2014 at 10:01:08AM +0200, Stephane Eranian wrote:
> On Thu, Oct 23, 2014 at 9:19 AM, Jiri Olsa <jolsa@redhat.com> wrote:
> > On Wed, Oct 22, 2014 at 02:31:51PM +0200, Jiri Olsa wrote:
> >> On Thu, Oct 09, 2014 at 06:34:40PM +0200, Stephane Eranian wrote:
> >> > From: Maria Dimakopoulou <maria.n.dimakopoulou@gmail.com>
SNIP
> >> > + for_each_set_bit(i, cx->idxmsk, X86_PMC_IDX_MAX) {
> >> > + /*
> >> > + * exclusive event in sibling counter
> >> > + * our corresponding counter cannot be used
> >> > + * regardless of our event
> >> > + */
> >> > + if (xl->state[i] == INTEL_EXCL_EXCLUSIVE)
> >> > + __clear_bit(i, cx->idxmsk);
> >>
> >> if we want to check sibling counter, shouldn't we check xlo->state[i] instead? like
> >>
> >> if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE)
> >> __clear_bit(i, cx->idxmsk);
> >>
> >>
> >> and also in condition below?
> >
> > any comment on this? I'm curious, because it'd enlighten me
> > on how this is supposed to work ;-)
> >
> > I dont understand why you update the sibling's counter state instead
> > of the current cpuc->excl_thread_id HT, like in intel_commit_scheduling
> > while you hold lock for the current HT state
> >
> > could you please comment, I must be missing something
> >
> Yes, it is a bit confusing. It comes down that what the state represents.
> Let me explain.
>
> In get_constraints(), you compute the bitmask of possible counters by looking
> at your own state in states[tid] (xl).
>
> In commit_constraint(), the scheduler has picked counters and you need to commit
> the changes. But you don't update your state, you update your
> sibling's state. Why?
> Because of the bug, what you use influences what the sibling can measure. So you
> update the sibling's state to reflect its new constraint. When the
> sibling calls get_constraint()
> it will harvest the new constraints automatically.
>
> Example:
>
> HT0 wants to program a MEM (corrupting) event, it gathers its
> constraints from get_constraints().
> The mask is, let's say, 0x3. The scheduler picks counter0. Then, in
> commit_constraints(), you need
> to mark *HT1*'s counter0 in exclusive mode, i.e., it cannot be used
> anymore on that thread.
ah, I translated the INTEL_EXCL_EXCLUSIVE state as "here's the exclusive
event, sibling HT is forbiden to schedule in this counter (slot)"
cool, thanks
jirka
next prev parent reply other threads:[~2014-10-23 8:14 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-09 16:34 [PATCH v2 0/12] perf/x86: implement HT leak workaround for SNB/IVB/HSW Stephane Eranian
2014-10-09 16:34 ` [PATCH v2 01/12] perf,x86: rename er_flags to flags Stephane Eranian
2014-10-09 16:34 ` [PATCH v2 02/12] perf/x86: vectorize cpuc->kfree_on_online Stephane Eranian
2014-10-09 16:34 ` [PATCH v2 03/12] perf/x86: add 3 new scheduling callbacks Stephane Eranian
2014-10-09 16:34 ` [PATCH v2 04/12] perf/x86: add index param to get_event_constraint() callback Stephane Eranian
2014-10-09 16:34 ` [PATCH v2 05/12] perf/x86: add cross-HT counter exclusion infrastructure Stephane Eranian
2014-10-21 11:17 ` Peter Zijlstra
2014-10-21 11:18 ` Peter Zijlstra
2014-10-22 15:07 ` Jiri Olsa
2014-10-22 17:25 ` Stephane Eranian
2014-10-23 7:14 ` Jiri Olsa
2014-10-09 16:34 ` [PATCH v2 06/12] perf/x86: implement cross-HT corruption bug workaround Stephane Eranian
2014-10-22 12:31 ` Jiri Olsa
2014-10-23 7:19 ` Jiri Olsa
2014-10-23 8:01 ` Stephane Eranian
2014-10-23 8:13 ` Jiri Olsa [this message]
2014-10-09 16:34 ` [PATCH v2 07/12] perf/x86: enforce HT bug workaround for SNB/IVB/HSW Stephane Eranian
2014-10-09 16:34 ` [PATCH v2 08/12] perf/x86: enforce HT bug workaround with PEBS " Stephane Eranian
2014-10-09 16:34 ` [PATCH v2 09/12] perf/x86: fix intel_get_event_constraints() for dynamic constraints Stephane Eranian
2014-10-09 16:34 ` [PATCH v2 10/12] watchdog: add watchdog enable/disable all functions Stephane Eranian
2014-10-09 16:34 ` [PATCH v2 11/12] perf/x86: make HT bug workaround conditioned on HT enabled Stephane Eranian
2014-10-22 13:27 ` Jiri Olsa
2014-10-22 14:36 ` Stephane Eranian
2014-10-22 14:58 ` Jiri Olsa
2014-10-22 16:42 ` Stephane Eranian
2014-10-09 16:34 ` [PATCH v2 12/12] perf/x86: add syfs entry to disable HT bug workaround Stephane Eranian
2014-10-21 11:25 ` [PATCH v2 0/12] perf/x86: implement HT leak workaround for SNB/IVB/HSW Peter Zijlstra
2014-10-21 12:28 ` Stephane Eranian
2014-10-21 13:03 ` Peter Zijlstra
2014-10-21 13:08 ` Stephane Eranian
2014-10-22 9:12 ` Peter Zijlstra
2014-10-22 21:04 ` Stephane Eranian
2014-10-23 8:53 ` Peter Zijlstra
2014-10-23 8:57 ` Stephane Eranian
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