From: Rob Herring <robh@kernel.org>
To: Richard Leitner <richard.leitner@skidata.com>
Cc: fugang.duan@nxp.com, mark.rutland@arm.com,
netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dev@g0hl1n.net
Subject: Re: [PATCH 2/2] net: ethernet: fsl: add phy reset after clk enable option
Date: Mon, 10 Jul 2017 08:26:47 -0500 [thread overview]
Message-ID: <20170710132647.evisnuc46vbxmg2e@rob-hp-laptop> (raw)
In-Reply-To: <1499346330-12166-2-git-send-email-richard.leitner@skidata.com>
On Thu, Jul 06, 2017 at 03:05:30PM +0200, Richard Leitner wrote:
> Some PHYs (for example the LAN8710) doesn't allow turning the clocks off
> and on again without reset (according to their datasheet). Exactly this
> behaviour was introduced for power saving reasons by commit e8fcfcd5684a
> ("net: fec: optimize the clock management to save power")
> Therefore add a devictree option to perform a PHY reset and
> configuration after every clock enable.
>
> For a better understanding here's a outline of the time response of the
> clock and reset lines before and after this patch:
>
> v--fec_probe() v--fec_enet_open()
> v v
> w/o patch eCLK: ___||||||||____________________|||||||||||||||||
> w/o patch nRST: ----__------------------------------------------
> w/o patch CONF: _______XX_______________________________________
>
> w/ patch eCLK: ___||||||||____________________|||||||||||||||||
> w/ patch nRST: ----__--------------------------__--------------
> w/ patch CONF: _______XX__________________________XX___________
> ^ ^
> ^--fec_probe() ^--fec_enet_open()
>
> In our case this problem does occur at about every 10th to 50th POR of
> an LAN8710 connected to an i.MX6 SoC. The typical symptom of this
> problem is a "swinging" ethernet link. Similar issues were experienced
> by users of the NXP forum:
> https://community.nxp.com/thread/389902
> https://community.nxp.com/message/309354
> With this patch applied the issue didn't occur for at least a few
> hundred PORs of our board.
>
> Fixes: e8fcfcd5684a ("net: fec: optimize the clock management to sa...")
> Signed-off-by: Richard Leitner <richard.leitner@skidata.com>
> ---
> Documentation/devicetree/bindings/net/fsl-fec.txt | 3 +++
> drivers/net/ethernet/freescale/fec.h | 1 +
> drivers/net/ethernet/freescale/fec_main.c | 16 ++++++++++++++++
> 3 files changed, 20 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt
> index 6f55bdd..1766579 100644
> --- a/Documentation/devicetree/bindings/net/fsl-fec.txt
> +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
> @@ -23,6 +23,9 @@ Optional properties:
> - phy-handle : phandle to the PHY device connected to this device.
> - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
> Use instead of phy-handle.
> +- phy-reset-after-clk-enable : If present then a phy reset and configuration
> + will be performed everytime after the clocks are enabled. This is required
> + for some PHYs to work properly.
Maybe this is not needed based on the discussion, but just to make
sure. Since this is a property of the phy, it should be implied from the
phy's compatible string.
Rob
prev parent reply other threads:[~2017-07-10 13:26 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-06 13:05 [PATCH 1/2] net: ethernet: freescale: simplify fec_reset_phy Richard Leitner
2017-07-06 13:05 ` [PATCH 2/2] net: ethernet: fsl: add phy reset after clk enable option Richard Leitner
2017-07-06 13:55 ` Andrew Lunn
2017-07-06 14:33 ` Richard Leitner
2017-07-07 5:30 ` Andy Duan
2017-07-07 5:50 ` Richard Leitner
2017-07-07 7:03 ` Andy Duan
2017-07-07 9:52 ` Richard Leitner
2017-07-07 11:08 ` Andy Duan
2017-07-07 11:16 ` Richard Leitner
2017-07-07 14:00 ` Andrew Lunn
2017-07-12 9:21 ` Richard Leitner
2017-07-12 13:40 ` Andrew Lunn
2017-07-10 13:26 ` Rob Herring [this message]
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