* [PATCH 0/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag and improve Denali driver
@ 2017-09-12 2:37 Masahiro Yamada
2017-09-12 2:37 ` [PATCH 1/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag Masahiro Yamada
2017-09-12 2:37 ` [PATCH 2/2] mtd: nand: denali: support two row address cycle devices Masahiro Yamada
0 siblings, 2 replies; 4+ messages in thread
From: Masahiro Yamada @ 2017-09-12 2:37 UTC (permalink / raw)
To: linux-mtd
Cc: Masahiro Yamada, Cyrille Pitchen, Josh Wu, Wan ZongShun,
linux-kernel, Boris Brezillon, Marek Vasut, Brian Norris,
Richard Weinberger, David Woodhouse, Wenyou Yang,
linux-arm-kernel
Currently, Denali NAND driver always expects 3 row address cycle
devices because the driver init code hard-code the register setting.
I will fix it in 2/2.
Many drivers check chip->chipsize if the third row address cycle
is needed or not. This is not nice because 32MB, 128MB are
magic numbers. nand_scan_ident can decide it and provide a
driver-friendly flag.
1/2 is touching verious drivers.
I hope Acked-by from driver maintainers if this change looks good.
Masahiro Yamada (2):
mtd: nand: introduce NAND_ROW_ADDR_3 flag
mtd: nand: denali: support two row address cycle devices
drivers/mtd/nand/atmel/nand-controller.c | 3 +--
drivers/mtd/nand/au1550nd.c | 3 +--
drivers/mtd/nand/denali.c | 4 ++--
drivers/mtd/nand/diskonchip.c | 3 +--
drivers/mtd/nand/hisi504_nand.c | 3 +--
drivers/mtd/nand/mxc_nand.c | 3 +--
drivers/mtd/nand/nand_base.c | 9 +++++----
drivers/mtd/nand/nuc900_nand.c | 2 +-
include/linux/mtd/rawnand.h | 3 +++
9 files changed, 16 insertions(+), 17 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag
2017-09-12 2:37 [PATCH 0/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag and improve Denali driver Masahiro Yamada
@ 2017-09-12 2:37 ` Masahiro Yamada
2017-09-13 1:20 ` kbuild test robot
2017-09-12 2:37 ` [PATCH 2/2] mtd: nand: denali: support two row address cycle devices Masahiro Yamada
1 sibling, 1 reply; 4+ messages in thread
From: Masahiro Yamada @ 2017-09-12 2:37 UTC (permalink / raw)
To: linux-mtd
Cc: Masahiro Yamada, Cyrille Pitchen, Josh Wu, Wan ZongShun,
linux-kernel, Boris Brezillon, Marek Vasut, Brian Norris,
Richard Weinberger, David Woodhouse, Wenyou Yang,
linux-arm-kernel
Several drivers check ->chipsize to see if the third row address cycle
is needed. Instead of embedding magic sizes such as 32MB, 128MB in
drivers, introduce a new flag NAND_ROW_ADDR_3 for clean-up. Since
nand_scan_ident() knows well about the device, it can handle this
properly. The flag is set if the row address bit width is greater
than 16.
Delete comments such as "One more address cycle for ..." because
intention is now clear enough from the code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/mtd/nand/atmel/nand-controller.c | 3 +--
drivers/mtd/nand/au1550nd.c | 3 +--
drivers/mtd/nand/diskonchip.c | 3 +--
drivers/mtd/nand/hisi504_nand.c | 3 +--
drivers/mtd/nand/mxc_nand.c | 3 +--
drivers/mtd/nand/nand_base.c | 9 +++++----
drivers/mtd/nand/nuc900_nand.c | 2 +-
include/linux/mtd/rawnand.h | 3 +++
8 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/mtd/nand/atmel/nand-controller.c b/drivers/mtd/nand/atmel/nand-controller.c
index f25eca7..7bc8d20 100644
--- a/drivers/mtd/nand/atmel/nand-controller.c
+++ b/drivers/mtd/nand/atmel/nand-controller.c
@@ -718,8 +718,7 @@ static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
nc->op.addrs[nc->op.naddrs++] = page;
nc->op.addrs[nc->op.naddrs++] = page >> 8;
- if ((mtd->writesize > 512 && chip->chipsize > SZ_128M) ||
- (mtd->writesize <= 512 && chip->chipsize > SZ_32M))
+ if (chip->options & NAND_ROW_ADDR_3)
nc->op.addrs[nc->op.naddrs++] = page >> 16;
}
}
diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c
index 9d4a28f..8ab827e 100644
--- a/drivers/mtd/nand/au1550nd.c
+++ b/drivers/mtd/nand/au1550nd.c
@@ -331,8 +331,7 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
ctx->write_byte(mtd, (u8)(page_addr >> 8));
- /* One more address cycle for devices > 32MiB */
- if (this->chipsize > (32 << 20))
+ if (this->options & NAND_ROW_ADDR_3)
ctx->write_byte(mtd,
((page_addr >> 16) & 0x0f));
}
diff --git a/drivers/mtd/nand/diskonchip.c b/drivers/mtd/nand/diskonchip.c
index c3aa53c..72671dc 100644
--- a/drivers/mtd/nand/diskonchip.c
+++ b/drivers/mtd/nand/diskonchip.c
@@ -705,8 +705,7 @@ static void doc2001plus_command(struct mtd_info *mtd, unsigned command, int colu
if (page_addr != -1) {
WriteDOC((unsigned char)(page_addr & 0xff), docptr, Mplus_FlashAddress);
WriteDOC((unsigned char)((page_addr >> 8) & 0xff), docptr, Mplus_FlashAddress);
- /* One more address cycle for higher density devices */
- if (this->chipsize & 0x0c000000) {
+ if (this->options & NAND_ROW_ADDR_3) {
WriteDOC((unsigned char)((page_addr >> 16) & 0x0f), docptr, Mplus_FlashAddress);
printk("high density\n");
}
diff --git a/drivers/mtd/nand/hisi504_nand.c b/drivers/mtd/nand/hisi504_nand.c
index d9ee1a7..0ded7f4 100644
--- a/drivers/mtd/nand/hisi504_nand.c
+++ b/drivers/mtd/nand/hisi504_nand.c
@@ -432,8 +432,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr)
host->addr_value[0] |= (page_addr & 0xffff)
<< (host->addr_cycle * 8);
host->addr_cycle += 2;
- /* One more address cycle for devices > 128MiB */
- if (chip->chipsize > (128 << 20)) {
+ if (chip->->options & NAND_ROW_ADDR_3) {
host->addr_cycle += 1;
if (host->command == NAND_CMD_ERASE1)
host->addr_value[0] |= ((page_addr >> 16) & 0xff) << 16;
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 53e5e03..bacdd04 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -859,8 +859,7 @@ static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
host->devtype_data->send_addr(host,
(page_addr >> 8) & 0xff, true);
} else {
- /* One more address cycle for higher density devices */
- if (mtd->size >= 0x4000000) {
+ if (nand_chip->options & NAND_ROW_ADDR_3) {
/* paddr_8 - paddr_15 */
host->devtype_data->send_addr(host,
(page_addr >> 8) & 0xff,
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index bcc8cef1..3bc4404 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -727,8 +727,7 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
chip->cmd_ctrl(mtd, page_addr, ctrl);
ctrl &= ~NAND_CTRL_CHANGE;
chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
- /* One more address cycle for devices > 32MiB */
- if (chip->chipsize > (32 << 20))
+ if (chip->options & NAND_ROW_ADDR_3)
chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
}
chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
@@ -854,8 +853,7 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
chip->cmd_ctrl(mtd, page_addr, ctrl);
chip->cmd_ctrl(mtd, page_addr >> 8,
NAND_NCE | NAND_ALE);
- /* One more address cycle for devices > 128MiB */
- if (chip->chipsize > (128 << 20))
+ if (chip->options & NAND_ROW_ADDR_3)
chip->cmd_ctrl(mtd, page_addr >> 16,
NAND_NCE | NAND_ALE);
}
@@ -4000,6 +3998,9 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
chip->chip_shift += 32 - 1;
}
+ if (chip->chip_shift - chip->page_shift > 16)
+ chip->options |= NAND_ROW_ADDR_3;
+
chip->badblockbits = 8;
chip->erase = single_erase;
diff --git a/drivers/mtd/nand/nuc900_nand.c b/drivers/mtd/nand/nuc900_nand.c
index 7bb4d2e..af5b32c9 100644
--- a/drivers/mtd/nand/nuc900_nand.c
+++ b/drivers/mtd/nand/nuc900_nand.c
@@ -154,7 +154,7 @@ static void nuc900_nand_command_lp(struct mtd_info *mtd, unsigned int command,
if (page_addr != -1) {
write_addr_reg(nand, page_addr);
- if (chip->chipsize > (128 << 20)) {
+ if (chip->options & NAND_ROW_ADDR_3) {
write_addr_reg(nand, page_addr >> 8);
write_addr_reg(nand, page_addr >> 16 | ENDADDR);
} else {
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 2b05f42..749bb08 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -177,6 +177,9 @@ enum nand_ecc_algo {
*/
#define NAND_NEED_SCRAMBLING 0x00002000
+/* Device needs 3rd row address cycle */
+#define NAND_ROW_ADDR_3 0x00004000
+
/* Options valid for Samsung large page devices */
#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
--
2.7.4
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/2] mtd: nand: denali: support two row address cycle devices
2017-09-12 2:37 [PATCH 0/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag and improve Denali driver Masahiro Yamada
2017-09-12 2:37 ` [PATCH 1/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag Masahiro Yamada
@ 2017-09-12 2:37 ` Masahiro Yamada
1 sibling, 0 replies; 4+ messages in thread
From: Masahiro Yamada @ 2017-09-12 2:37 UTC (permalink / raw)
To: linux-mtd
Cc: Masahiro Yamada, Cyrille Pitchen, linux-kernel, Boris Brezillon,
Marek Vasut, Brian Norris, Richard Weinberger, David Woodhouse
The register TWO_ROW_ADDR_CYCLES specifies the number of row address
cycles of the device, but it is fixed to 0 in the driver init code
(i.e. always 3 row address cycles).
Reflect the result of nand_scan_ident() to the register setting
in order to support 2 row address cycle devices.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/mtd/nand/denali.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 3087b0b..aefdc83 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -1137,8 +1137,6 @@ static void denali_hw_init(struct denali_nand_info *denali)
iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER);
- /* Should set value for these registers when init */
- iowrite32(0, denali->reg + TWO_ROW_ADDR_CYCLES);
iowrite32(1, denali->reg + ECC_ENABLE);
}
@@ -1379,6 +1377,8 @@ int denali_init(struct denali_nand_info *denali)
denali->reg + PAGES_PER_BLOCK);
iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,
denali->reg + DEVICE_WIDTH);
+ iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG,
+ denali->reg + TWO_ROW_ADDR_CYCLES);
iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE);
iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE);
--
2.7.4
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag
2017-09-12 2:37 ` [PATCH 1/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag Masahiro Yamada
@ 2017-09-13 1:20 ` kbuild test robot
0 siblings, 0 replies; 4+ messages in thread
From: kbuild test robot @ 2017-09-13 1:20 UTC (permalink / raw)
To: Masahiro Yamada
Cc: kbuild-all, linux-mtd, Masahiro Yamada, Cyrille Pitchen, Josh Wu,
Wan ZongShun, linux-kernel, Boris Brezillon, Marek Vasut,
Brian Norris, Richard Weinberger, David Woodhouse, Wenyou Yang,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 2366 bytes --]
Hi Masahiro,
[auto build test ERROR on l2-mtd-boris/nand/next]
[also build test ERROR on v4.13 next-20170912]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Masahiro-Yamada/mtd-nand-introduce-NAND_ROW_ADDR_3-flag-and-improve-Denali-driver/20170913-084354
base: git://git.infradead.org/l2-mtd.git nand/next
config: xtensa-allyesconfig (attached as .config)
compiler: xtensa-linux-gcc (GCC) 4.9.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=xtensa
All errors (new ones prefixed by >>):
drivers/mtd/nand/hisi504_nand.c: In function 'set_addr':
>> drivers/mtd/nand/hisi504_nand.c:435:13: error: expected identifier before '->' token
if (chip->->options & NAND_ROW_ADDR_3) {
^
vim +435 drivers/mtd/nand/hisi504_nand.c
410
411 static void set_addr(struct mtd_info *mtd, int column, int page_addr)
412 {
413 struct nand_chip *chip = mtd_to_nand(mtd);
414 struct hinfc_host *host = nand_get_controller_data(chip);
415 unsigned int command = host->command;
416
417 host->addr_cycle = 0;
418 host->addr_value[0] = 0;
419 host->addr_value[1] = 0;
420
421 /* Serially input address */
422 if (column != -1) {
423 /* Adjust columns for 16 bit buswidth */
424 if (chip->options & NAND_BUSWIDTH_16 &&
425 !nand_opcode_8bits(command))
426 column >>= 1;
427
428 host->addr_value[0] = column & 0xffff;
429 host->addr_cycle = 2;
430 }
431 if (page_addr != -1) {
432 host->addr_value[0] |= (page_addr & 0xffff)
433 << (host->addr_cycle * 8);
434 host->addr_cycle += 2;
> 435 if (chip->->options & NAND_ROW_ADDR_3) {
436 host->addr_cycle += 1;
437 if (host->command == NAND_CMD_ERASE1)
438 host->addr_value[0] |= ((page_addr >> 16) & 0xff) << 16;
439 else
440 host->addr_value[1] |= ((page_addr >> 16) & 0xff);
441 }
442 }
443 }
444
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 51034 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
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2017-09-12 2:37 [PATCH 0/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag and improve Denali driver Masahiro Yamada
2017-09-12 2:37 ` [PATCH 1/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag Masahiro Yamada
2017-09-13 1:20 ` kbuild test robot
2017-09-12 2:37 ` [PATCH 2/2] mtd: nand: denali: support two row address cycle devices Masahiro Yamada
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