[PATCH 0/3] Drop pv_cpu_ops::wbinvd() and bring support of WBNOINVD

[PATCH 0/3] Drop pv_cpu_ops::wbinvd() and bring support of WBNOINVD

[Kirill A. Shutemov]

Instruction Set Extensions and Future Features Programming Reference[1] v031
introduces new WBNOINVD instruction.

The WBNOINVD instruction writes back all modified cache lines in the
processor’s internal cache to main memory and does not invalidate
(flush) the internal caches.

The patchset removes WBINVD-related dead code, add CPUID flag for the new
instruction and instrumentation to call it.

No users for the code introduced, but we are planning to use it for
Multi-Key Total Memory Encryption[2] enabling.

[1] https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
[2] https://software.intel.com/sites/default/files/managed/a5/16/Multi-Key-Total-Memory-Encryption-Spec.pdf

Kirill A. Shutemov (3):
  x86/paravirt: Drop pv_cpu_ops::wbinvd()
  x86/cpufeatures: Add WBNOINVD cpufeature
  x86/asm: Add support for WBNOINVD instruction

 arch/x86/include/asm/cpufeatures.h    |  3 ++-
 arch/x86/include/asm/paravirt.h       |  5 -----
 arch/x86/include/asm/paravirt_types.h |  1 -
 arch/x86/include/asm/smp.h            | 10 ++++++++++
 arch/x86/include/asm/special_insns.h  | 12 ++++++------
 arch/x86/kernel/paravirt.c            |  1 -
 arch/x86/kernel/paravirt_patch_64.c   |  2 --
 arch/x86/lib/cache-smp.c              | 17 +++++++++++++++++
 arch/x86/xen/enlighten_pv.c           |  2 --
 9 files changed, 35 insertions(+), 18 deletions(-)

-- 
2.15.1

[PATCH 1/3] x86/paravirt: Drop pv_cpu_ops::wbinvd()

[Kirill A. Shutemov]

lguest was the last user of non-native pv_cpu_ops::wbinvd()
implementation. lguest has gone and we can drop support of the
operation.

Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
---
 arch/x86/include/asm/paravirt.h       | 5 -----
 arch/x86/include/asm/paravirt_types.h | 1 -
 arch/x86/include/asm/special_insns.h  | 7 +------
 arch/x86/kernel/paravirt.c            | 1 -
 arch/x86/kernel/paravirt_patch_64.c   | 2 --
 arch/x86/xen/enlighten_pv.c           | 2 --
 6 files changed, 1 insertion(+), 17 deletions(-)

diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index 892df375b615..4d6bd43733f9 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -98,11 +98,6 @@ static inline void halt(void)
 	PVOP_VCALL0(pv_irq_ops.halt);
 }
 
-static inline void wbinvd(void)
-{
-	PVOP_VCALL0(pv_cpu_ops.wbinvd);
-}
-
 #define get_kernel_rpl()  (pv_info.kernel_rpl)
 
 static inline u64 paravirt_read_msr(unsigned msr)
diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h
index 6ec54d01972d..1d003607dd1c 100644
--- a/arch/x86/include/asm/paravirt_types.h
+++ b/arch/x86/include/asm/paravirt_types.h
@@ -138,7 +138,6 @@ struct pv_cpu_ops {
 
 	void (*set_iopl_mask)(unsigned mask);
 
-	void (*wbinvd)(void);
 	void (*io_delay)(void);
 
 	/* cpuid emulation, mostly so that caps bits can be disabled */
diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h
index 317fc59b512c..0d9c28a7833d 100644
--- a/arch/x86/include/asm/special_insns.h
+++ b/arch/x86/include/asm/special_insns.h
@@ -129,7 +129,7 @@ static inline void __write_pkru(u32 pkru)
 }
 #endif
 
-static inline void native_wbinvd(void)
+static inline void wbinvd(void)
 {
 	asm volatile("wbinvd": : :"memory");
 }
@@ -184,11 +184,6 @@ static inline void __write_cr4(unsigned long x)
 	native_write_cr4(x);
 }
 
-static inline void wbinvd(void)
-{
-	native_wbinvd();
-}
-
 #ifdef CONFIG_X86_64
 
 static inline unsigned long read_cr8(void)
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index 041096bdef86..5ce5bf145e36 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -342,7 +342,6 @@ __visible struct pv_cpu_ops pv_cpu_ops = {
 	.read_cr8 = native_read_cr8,
 	.write_cr8 = native_write_cr8,
 #endif
-	.wbinvd = native_wbinvd,
 	.read_msr = native_read_msr,
 	.write_msr = native_write_msr,
 	.read_msr_safe = native_read_msr_safe,
diff --git a/arch/x86/kernel/paravirt_patch_64.c b/arch/x86/kernel/paravirt_patch_64.c
index 9edadabf04f6..ee81ce4593d4 100644
--- a/arch/x86/kernel/paravirt_patch_64.c
+++ b/arch/x86/kernel/paravirt_patch_64.c
@@ -10,7 +10,6 @@ DEF_NATIVE(pv_irq_ops, save_fl, "pushfq; popq %rax");
 DEF_NATIVE(pv_mmu_ops, read_cr2, "movq %cr2, %rax");
 DEF_NATIVE(pv_mmu_ops, read_cr3, "movq %cr3, %rax");
 DEF_NATIVE(pv_mmu_ops, write_cr3, "movq %rdi, %cr3");
-DEF_NATIVE(pv_cpu_ops, wbinvd, "wbinvd");
 
 DEF_NATIVE(pv_cpu_ops, usergs_sysret64, "swapgs; sysretq");
 DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs");
@@ -59,7 +58,6 @@ unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
 		PATCH_SITE(pv_mmu_ops, read_cr2);
 		PATCH_SITE(pv_mmu_ops, read_cr3);
 		PATCH_SITE(pv_mmu_ops, write_cr3);
-		PATCH_SITE(pv_cpu_ops, wbinvd);
 #if defined(CONFIG_PARAVIRT_SPINLOCKS)
 		case PARAVIRT_PATCH(pv_lock_ops.queued_spin_unlock):
 			if (pv_is_native_spin_unlock()) {
diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c
index c047f42552e1..5ea6bb0bd3e5 100644
--- a/arch/x86/xen/enlighten_pv.c
+++ b/arch/x86/xen/enlighten_pv.c
@@ -1055,8 +1055,6 @@ static const struct pv_cpu_ops xen_cpu_ops __initconst = {
 	.write_cr8 = xen_write_cr8,
 #endif
 
-	.wbinvd = native_wbinvd,
-
 	.read_msr = xen_read_msr,
 	.write_msr = xen_write_msr,
 
-- 
2.15.1

[PATCH 2/3] x86/cpufeatures: Add WBNOINVD cpufeature

[Kirill A. Shutemov]

CPUID.0x80000008:EBX[9] indicates whether CPU supports WBNOINVD
instruction.

The WBNOINVD instruction writes back all modified cache lines in the
processor’s internal cache to main memory and does not invalidate
(flush) the internal caches.

Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
---
 arch/x86/include/asm/cpufeatures.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 25b9375c1484..125b82c7f7cb 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -267,10 +267,11 @@
 #define X86_FEATURE_CQM_MBM_TOTAL	(12*32+ 1) /* LLC Total MBM monitoring */
 #define X86_FEATURE_CQM_MBM_LOCAL	(12*32+ 2) /* LLC Local MBM monitoring */
 
-/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
+/* CPU features, CPUID level 0x80000008 (EBX), word 13 */
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
 #define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */
 #define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */
+#define X86_FEATURE_WBNOINVD		(13*32+ 9) /* WBNOINVD instruction */
 
 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
 #define X86_FEATURE_DTHERM		(14*32+ 0) /* Digital Thermal Sensor */
-- 
2.15.1

Re: [PATCH 2/3] x86/cpufeatures: Add WBNOINVD cpufeature

[Thomas Gleixner]

[-- Attachment #1: Type: text/plain, Size: 457 bytes --]

On Fri, 19 Jan 2018, Kirill A. Shutemov wrote:

> CPUID.0x80000008:EBX[9] indicates whether CPU supports WBNOINVD
> instruction.
> 
> The WBNOINVD instruction writes back all modified cache lines in the
> processor’s internal cache to main memory and does not invalidate
> (flush) the internal caches.

That's describing what that instruction does. Could you please explain why
this is useful and what kind of usage you envision for that.

Thanks,

	tglx

[PATCH 3/3] x86/asm: Add support for WBNOINVD instruction

[Kirill A. Shutemov]

This patch implements infrastructure to call WBNOINVD instruction.
The basic idea is to match what we have for WBINVD.

The instruction is defined as WBINVD with REP (0xf3) prefix. If the
machine doesn't support the instruction the prefix will be ignored and
we would fallback to WBINVD.

Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
---
 arch/x86/include/asm/smp.h           | 10 ++++++++++
 arch/x86/include/asm/special_insns.h |  5 +++++
 arch/x86/lib/cache-smp.c             | 17 +++++++++++++++++
 3 files changed, 32 insertions(+)

diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h
index 461f53d27708..cadaf5e0ea92 100644
--- a/arch/x86/include/asm/smp.h
+++ b/arch/x86/include/asm/smp.h
@@ -140,6 +140,8 @@ void native_play_dead(void);
 void play_dead_common(void);
 void wbinvd_on_cpu(int cpu);
 int wbinvd_on_all_cpus(void);
+void wbnoinvd_on_cpu(int cpu);
+int wbnoinvd_on_all_cpus(void);
 
 void native_send_call_func_ipi(const struct cpumask *mask);
 void native_send_call_func_single_ipi(int cpu);
@@ -170,6 +172,14 @@ static inline int wbinvd_on_all_cpus(void)
 	wbinvd();
 	return 0;
 }
+
+#define wbnoinvd_on_cpu(cpu)     wbnoinvd()
+static inline int wbnoinvd_on_all_cpus(void)
+{
+	wbnoinvd();
+	return 0;
+}
+
 #define smp_num_siblings	1
 #endif /* CONFIG_SMP */
 
diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h
index 0d9c28a7833d..03d01446fff6 100644
--- a/arch/x86/include/asm/special_insns.h
+++ b/arch/x86/include/asm/special_insns.h
@@ -134,6 +134,11 @@ static inline void wbinvd(void)
 	asm volatile("wbinvd": : :"memory");
 }
 
+static inline void wbnoinvd(void)
+{
+	asm volatile(".byte 0xf3; wbinvd": : :"memory");
+}
+
 extern asmlinkage void native_load_gs_index(unsigned);
 
 static inline unsigned long __read_cr4(void)
diff --git a/arch/x86/lib/cache-smp.c b/arch/x86/lib/cache-smp.c
index 1811fa4a1b1a..e881741d0367 100644
--- a/arch/x86/lib/cache-smp.c
+++ b/arch/x86/lib/cache-smp.c
@@ -18,3 +18,20 @@ int wbinvd_on_all_cpus(void)
 	return on_each_cpu(__wbinvd, NULL, 1);
 }
 EXPORT_SYMBOL(wbinvd_on_all_cpus);
+
+static void __wbnoinvd(void *dummy)
+{
+	wbnoinvd();
+}
+
+void wbnoinvd_on_cpu(int cpu)
+{
+	smp_call_function_single(cpu, __wbnoinvd, NULL, 1);
+}
+EXPORT_SYMBOL(wbnoinvd_on_cpu);
+
+int wbnoinvd_on_all_cpus(void)
+{
+	return on_each_cpu(__wbnoinvd, NULL, 1);
+}
+EXPORT_SYMBOL(wbnoinvd_on_all_cpus);
-- 
2.15.1

Re: [PATCH 3/3] x86/asm: Add support for WBNOINVD instruction

[Thomas Gleixner]

On Fri, 19 Jan 2018, Kirill A. Shutemov wrote:

> This patch implements infrastructure to call WBNOINVD instruction.

grep 'This patch' Documentation/process/

> The basic idea is to match what we have for WBINVD.

Is it just an idea or is it actually doing it?

> The instruction is defined as WBINVD with REP (0xf3) prefix. If the
> machine doesn't support the instruction the prefix will be ignored and
> we would fallback to WBINVD.

We fallback? We do nothing.

The CPU ignores the prefix and falls back to WBINVD, right?

> +
> +#define wbnoinvd_on_cpu(cpu)     wbnoinvd()
> +static inline int wbnoinvd_on_all_cpus(void)

Bah. Please stop glueing defines in front of the function body. That's just
makes it harder to read.

Thanks,

	tglx