From: Marc Zyngier <marc.zyngier@arm.com>
To: linux-kernel@vger.kernel.org
Cc: Thomas Gleixner <tglx@linutronix.de>,
Ard Biesheuvel <ard.biesheuvel@linaro.org>,
Shanker Donthineni <shankerd@codeaurora.org>,
Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>,
MaJun <majun258@huawei.com>,
Laurentiu Tudor <laurentiu.tudor@nxp.com>,
Lei Zhang <zhang.lei@jp.fujitsu.com>
Subject: [PATCH 7/7] irqchip/gic-v3-its: Reduce minimum LPI allocation to 1 for PCI devices
Date: Wed, 20 Jun 2018 14:52:34 +0100 [thread overview]
Message-ID: <20180620135234.32101-8-marc.zyngier@arm.com> (raw)
In-Reply-To: <20180620135234.32101-1-marc.zyngier@arm.com>
Allocating a minimum of 32 LPIs per PCI device, let's reduce it to
be just 1, as most devices do not need that many interrupts.
We still have to special-case DevID 0, as there is plenty of broken
HW around where the PCI RID is not presented as a DevID to the ITS,
and all the devices are presented as DevID 0. In this case, we keep
the 32 minimal allocation.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
drivers/irqchip/irq-gic-v3-its-pci-msi.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its-pci-msi.c b/drivers/irqchip/irq-gic-v3-its-pci-msi.c
index 75c3cafabc6a..8d6d009d1d58 100644
--- a/drivers/irqchip/irq-gic-v3-its-pci-msi.c
+++ b/drivers/irqchip/irq-gic-v3-its-pci-msi.c
@@ -66,7 +66,7 @@ static int its_pci_msi_prepare(struct irq_domain *domain, struct device *dev,
{
struct pci_dev *pdev, *alias_dev;
struct msi_domain_info *msi_info;
- int alias_count = 0;
+ int alias_count = 0, minnvec = 1;
if (!dev_is_pci(dev))
return -EINVAL;
@@ -86,9 +86,17 @@ static int its_pci_msi_prepare(struct irq_domain *domain, struct device *dev,
/* ITS specific DeviceID, as the core ITS ignores dev. */
info->scratchpad[0].ul = pci_msi_domain_get_msi_rid(domain, pdev);
- /* Allocate at least 32 MSIs, and always as a power of 2 */
+ /*
+ * Always allocate a power of 2, and special case device 0 for
+ * broken systems where the DevID is not wired (and all devices
+ * appear as DevID 0). For that reason, we generously allocate a
+ * minimum of 32 MSIs for DevID 0. If you want more because all
+ * your devices are aliasing to DevID 0, consider fixing your HW.
+ */
nvec = max(nvec, alias_count);
- nvec = max_t(int, 32, roundup_pow_of_two(nvec));
+ if (!info->scratchpad[0].ul)
+ minnvec = 32;
+ nvec = max_t(int, minnvec, roundup_pow_of_two(nvec));
return msi_info->ops->msi_prepare(domain->parent, dev, nvec, info);
}
--
2.17.1
next prev parent reply other threads:[~2018-06-20 13:53 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-20 13:52 [PATCH 0/7] irqchip/gic-v3: LPI allocation refactoring Marc Zyngier
2018-06-20 13:52 ` [PATCH 1/7] irqchip/gic-v3-its: Refactor LPI allocator Marc Zyngier
2018-06-20 13:52 ` [PATCH 2/7] irqchip/gic-v3-its: Use full range of LPIs Marc Zyngier
2018-06-20 13:52 ` [PATCH 3/7] irqchip/gic-v3-its: Move minimum LPI requirements to individual busses Marc Zyngier
2018-06-20 13:52 ` [PATCH 4/7] irqchip/gic-v3-its: Drop chunk allocation compatibility Marc Zyngier
2018-06-20 13:52 ` [PATCH 5/7] irqchip/gic-v3: Expose GICD_TYPER in the rdist structure Marc Zyngier
2018-06-20 13:52 ` [PATCH 6/7] irqchip/gic-v3-its: Honor hypervisor enforced LPI range Marc Zyngier
2018-06-22 16:31 ` Shameerali Kolothum Thodi
2018-06-22 17:54 ` Marc Zyngier
2018-06-20 13:52 ` Marc Zyngier [this message]
2018-07-18 1:15 ` [PATCH 0/7] irqchip/gic-v3: LPI allocation refactoring Zhang, Lei
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