From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>,
Serge Semin <fancer.lancer@gmail.com>,
Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
Paul Burton <paulburton@kernel.org>,
Ralf Baechle <ralf@linux-mips.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Arnd Bergmann <arnd@arndb.de>, Rob Herring <robh+dt@kernel.org>,
<devicetree@vger.kernel.org>,
Thomas Bogendoerfer <tbogendoerfer@suse.de>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Huacai Chen <chenhc@lemote.com>,
Alexander Lobakin <alobakin@dlink.ru>,
Thomas Gleixner <tglx@linutronix.de>,
Vincenzo Frascino <vincenzo.frascino@arm.com>,
<linux-mips@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v3 13/14] mips: csrc-r4k: Mark R4K timer as unstable if CPU freq changes
Date: Thu, 21 May 2020 03:34:42 +0300 [thread overview]
Message-ID: <20200521003443.11385-14-Sergey.Semin@baikalelectronics.ru> (raw)
In-Reply-To: <20200521003443.11385-1-Sergey.Semin@baikalelectronics.ru>
Commit 07d69579e7fe ("MIPS: Don't register r4k sched clock when CPUFREQ
enabled") disabled the r4k-clock usage for scheduler ticks counting due
to the scheduler being non-tolerant for unstable clocks sources. For the
same reason the clock should be used in the system clocksource framework
with care. As soon as CPU frequency changes the clocksource framework
should be notified about this by marking the R4K timer being unstable
(which it really is, since the ticks rate has been changed synchronously
with the CPU frequency).
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
---
Changelog v3:
- Mark clocksource as unstable instead of lowering its rating.
---
arch/mips/Kconfig | 1 +
arch/mips/kernel/csrc-r4k.c | 40 +++++++++++++++++++++++++++++++++++++
2 files changed, 41 insertions(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b0eff203fbd8..c2911864fee1 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1154,6 +1154,7 @@ config CSRC_IOASIC
bool
config CSRC_R4K
+ select CLOCKSOURCE_WATCHDOG if CPU_FREQ
bool
config CSRC_SB1250
diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
index 437dda64fd7a..edc4afc080fa 100644
--- a/arch/mips/kernel/csrc-r4k.c
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -6,6 +6,7 @@
* Copyright (C) 2007 by Ralf Baechle
*/
#include <linux/clocksource.h>
+#include <linux/cpufreq.h>
#include <linux/init.h>
#include <linux/sched_clock.h>
@@ -65,6 +66,45 @@ static bool rdhwr_count_usable(void)
return false;
}
+#ifdef CONFIG_CPU_FREQ
+
+static bool __read_mostly r4k_clock_unstable;
+
+static void r4k_clocksource_unstable(char *reason)
+{
+ if (r4k_clock_unstable)
+ return;
+
+ r4k_clock_unstable = true;
+
+ pr_info("R4K timer is unstable due to %s\n", reason);
+
+ clocksource_mark_unstable(&clocksource_mips);
+}
+
+static int r4k_cpufreq_callback(struct notifier_block *nb,
+ unsigned long val, void *data)
+{
+ if (val == CPUFREQ_POSTCHANGE)
+ r4k_clocksource_unstable("CPU frequency change");
+
+ return 0;
+}
+
+static struct notifier_block r4k_cpufreq_notifier = {
+ .notifier_call = r4k_cpufreq_callback,
+};
+
+static int __init r4k_register_cpufreq_notifier(void)
+{
+ return cpufreq_register_notifier(&r4k_cpufreq_notifier,
+ CPUFREQ_TRANSITION_NOTIFIER);
+
+}
+core_initcall(r4k_register_cpufreq_notifier);
+
+#endif /* !CONFIG_CPU_FREQ */
+
int __init init_r4k_clocksource(void)
{
if (!cpu_has_counter || !mips_hpt_frequency)
--
2.25.1
next prev parent reply other threads:[~2020-05-21 0:35 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-21 0:34 [PATCH v3 00/14] mips: Prepare MIPS-arch code for Baikal-T1 SoC support Serge Semin
2020-05-21 0:34 ` [PATCH v3 01/14] dt-bindings: power: Convert mti,mips-cpc to DT schema Serge Semin
2020-05-21 0:34 ` [PATCH v3 02/14] dt-bindings: bus: Add MIPS CDMM controller Serge Semin
2020-05-21 0:34 ` [PATCH v3 03/14] mips: Add MIPS Release 5 support Serge Semin
2020-05-21 0:34 ` [PATCH v3 04/14] mips: Add MIPS Warrior P5600 support Serge Semin
2020-05-21 0:34 ` [PATCH v3 05/14] mips: Fix cpu_has_mips64r1/2 activation for MIPS32 CPUs Serge Semin
2020-05-21 0:34 ` [PATCH v3 06/14] mips: Add CP0 Write Merge config support Serge Semin
2020-05-21 0:34 ` [PATCH v3 07/14] mips: Add CONFIG/CONFIG6/Cause reg fields macro Serge Semin
2020-05-21 0:34 ` [PATCH v3 08/14] mips: MAAR: Use more precise address mask Serge Semin
2020-05-21 7:11 ` Thomas Bogendoerfer
2020-05-21 0:34 ` [PATCH v3 09/14] mips: Add CPS_NS16550_WIDTH config Serge Semin
2020-05-21 0:34 ` [PATCH v3 10/14] mips: cdmm: Add mti,mips-cdmm dtb node support Serge Semin
2020-05-21 0:34 ` [PATCH v3 11/14] bus: cdmm: Add MIPS R5 arch support Serge Semin
2020-05-21 10:25 ` Sergei Shtylyov
2020-05-21 12:58 ` Serge Semin
2020-05-21 15:44 ` Sergei Shtylyov
2020-05-21 0:34 ` [PATCH v3 12/14] mips: Add udelay lpj numbers adjustment Serge Semin
2020-05-21 0:34 ` Serge Semin [this message]
2020-05-21 0:34 ` [PATCH v3 14/14] mips: cevt-r4k: Update the r4k-clockevent frequency in sync with CPU Serge Semin
2020-05-21 0:42 ` [PATCH v3 00/14] mips: Prepare MIPS-arch code for Baikal-T1 SoC support Serge Semin
2020-05-21 7:14 ` Thomas Bogendoerfer
2020-05-21 7:30 ` Arnd Bergmann
2020-05-21 13:48 ` Serge Semin
2020-05-21 13:50 ` Serge Semin
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