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From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Paul Burton <paulburton@kernel.org>
Cc: "Serge Semin" <Sergey.Semin@baikalelectronics.ru>,
	"Serge Semin" <fancer.lancer@gmail.com>,
	"Alexey Malahov" <Alexey.Malahov@baikalelectronics.ru>,
	"Ralf Baechle" <ralf@linux-mips.org>,
	"Arnd Bergmann" <arnd@arndb.de>,
	"Rob Herring" <robh+dt@kernel.org>,
	devicetree@vger.kernel.org,
	"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v3 05/14] mips: Fix cpu_has_mips64r1/2 activation for MIPS32 CPUs
Date: Thu, 21 May 2020 03:34:34 +0300	[thread overview]
Message-ID: <20200521003443.11385-6-Sergey.Semin@baikalelectronics.ru> (raw)
In-Reply-To: <20200521003443.11385-1-Sergey.Semin@baikalelectronics.ru>

Commit 1aeba347b3a9 ("MIPS: Hardcode cpu_has_mips* where target ISA
allows") updated the cpu_has_mips* macro to be replaced with a constant
expression where it's possible. By mistake it wasn't done correctly
for cpu_has_mips64r1/cpu_has_mips64r2 macro. They are defined to
be replaced with conditional expression __isa_range_or_flag(), which
means either ISA revision being within the range or the corresponding
CPU options flag was set at the probe stage or both being true at the
same time. But the ISA level value doesn't indicate whether the ISA is
MIPS32 or MIPS64. Due to this if we select MIPS32r1 - MIPS32r5
architectures the __isa_range() macro will activate the
cpu_has_mips64rX flags, which is incorrect. In order to fix the
problem we make sure the 64bits CPU support is enabled by means of
checking the flag cpu_has_64bits aside with proper ISA range and specific
Revision flag being set.

Fixes: 1aeba347b3a9 ("MIPS: Hardcode cpu_has_mips* where target ISA allows")
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org

---

Changelog v3:
- Use cpu_has_64bits to make sure the CPU has 64bits ISA instead of
  creating and using a new macro __isa_range_and_flag().
---
 arch/mips/include/asm/cpu-features.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 8ecd13e3c9c2..556b460f31d8 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -291,10 +291,12 @@
 # define cpu_has_mips32r6	__isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6)
 #endif
 #ifndef cpu_has_mips64r1
-# define cpu_has_mips64r1	__isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1)
+# define cpu_has_mips64r1	(cpu_has_64bits && \
+				 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1))
 #endif
 #ifndef cpu_has_mips64r2
-# define cpu_has_mips64r2	__isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2)
+# define cpu_has_mips64r2	(cpu_has_64bits && \
+				 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2))
 #endif
 #ifndef cpu_has_mips64r5
 # define cpu_has_mips64r5	(cpu_has_64bits && \
-- 
2.25.1


  parent reply	other threads:[~2020-05-21  0:35 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-21  0:34 [PATCH v3 00/14] mips: Prepare MIPS-arch code for Baikal-T1 SoC support Serge Semin
2020-05-21  0:34 ` [PATCH v3 01/14] dt-bindings: power: Convert mti,mips-cpc to DT schema Serge Semin
2020-05-21  0:34 ` [PATCH v3 02/14] dt-bindings: bus: Add MIPS CDMM controller Serge Semin
2020-05-21  0:34 ` [PATCH v3 03/14] mips: Add MIPS Release 5 support Serge Semin
2020-05-21  0:34 ` [PATCH v3 04/14] mips: Add MIPS Warrior P5600 support Serge Semin
2020-05-21  0:34 ` Serge Semin [this message]
2020-05-21  0:34 ` [PATCH v3 06/14] mips: Add CP0 Write Merge config support Serge Semin
2020-05-21  0:34 ` [PATCH v3 07/14] mips: Add CONFIG/CONFIG6/Cause reg fields macro Serge Semin
2020-05-21  0:34 ` [PATCH v3 08/14] mips: MAAR: Use more precise address mask Serge Semin
2020-05-21  7:11   ` Thomas Bogendoerfer
2020-05-21  0:34 ` [PATCH v3 09/14] mips: Add CPS_NS16550_WIDTH config Serge Semin
2020-05-21  0:34 ` [PATCH v3 10/14] mips: cdmm: Add mti,mips-cdmm dtb node support Serge Semin
2020-05-21  0:34 ` [PATCH v3 11/14] bus: cdmm: Add MIPS R5 arch support Serge Semin
2020-05-21 10:25   ` Sergei Shtylyov
2020-05-21 12:58     ` Serge Semin
2020-05-21 15:44       ` Sergei Shtylyov
2020-05-21  0:34 ` [PATCH v3 12/14] mips: Add udelay lpj numbers adjustment Serge Semin
2020-05-21  0:34 ` [PATCH v3 13/14] mips: csrc-r4k: Mark R4K timer as unstable if CPU freq changes Serge Semin
2020-05-21  0:34 ` [PATCH v3 14/14] mips: cevt-r4k: Update the r4k-clockevent frequency in sync with CPU Serge Semin
2020-05-21  0:42 ` [PATCH v3 00/14] mips: Prepare MIPS-arch code for Baikal-T1 SoC support Serge Semin
2020-05-21  7:14   ` Thomas Bogendoerfer
2020-05-21  7:30     ` Arnd Bergmann
2020-05-21 13:48       ` Serge Semin
2020-05-21 13:50     ` Serge Semin

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