From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>,
Serge Semin <fancer.lancer@gmail.com>,
Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
Paul Burton <paulburton@kernel.org>,
Ralf Baechle <ralf@linux-mips.org>, Arnd Bergmann <arnd@arndb.de>,
Rob Herring <robh+dt@kernel.org>, <devicetree@vger.kernel.org>,
Zhou Yanjie <zhouyanjie@zoho.com>,
Paul Cercueil <paul@crapouillou.net>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
<linux-mips@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v3 08/14] mips: MAAR: Use more precise address mask
Date: Thu, 21 May 2020 03:34:37 +0300 [thread overview]
Message-ID: <20200521003443.11385-9-Sergey.Semin@baikalelectronics.ru> (raw)
In-Reply-To: <20200521003443.11385-1-Sergey.Semin@baikalelectronics.ru>
Indeed according to the MIPS32 Privileged Resource Architecgture the MAAR
pair register address field either takes [12:31] bits for non-XPA systems
and [12:55] otherwise. In any case the current address mask is just
wrong for 64-bit and 32-bits XPA chips. So lets extend it to 59-bits
of physical address value. This shall cover the 64-bits architecture and
systems with XPA enabled, and won't cause any problem for non-XPA 32-bit
systems, since address values exceeding the architecture specific MAAR
mask will be just truncated with setting zeros in the unsupported upper
bits.
Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
---
Changelog v3:
- In accordance with MIPS32/64 Privileged Resource Architecture Extend
the MAAR Addr mask to value [12:55] instead of P5600-specific [12:35].
---
arch/mips/include/asm/mipsregs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 039ebd913f00..30d9e28d01b0 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -775,7 +775,7 @@
/* MAAR bit definitions */
#define MIPS_MAAR_VH (_U64CAST_(1) << 63)
-#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
+#define MIPS_MAAR_ADDR GENMASK_ULL(55, 12)
#define MIPS_MAAR_ADDR_SHIFT 12
#define MIPS_MAAR_S (_ULCAST_(1) << 1)
#define MIPS_MAAR_VL (_ULCAST_(1) << 0)
--
2.25.1
next prev parent reply other threads:[~2020-05-21 0:35 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-21 0:34 [PATCH v3 00/14] mips: Prepare MIPS-arch code for Baikal-T1 SoC support Serge Semin
2020-05-21 0:34 ` [PATCH v3 01/14] dt-bindings: power: Convert mti,mips-cpc to DT schema Serge Semin
2020-05-21 0:34 ` [PATCH v3 02/14] dt-bindings: bus: Add MIPS CDMM controller Serge Semin
2020-05-21 0:34 ` [PATCH v3 03/14] mips: Add MIPS Release 5 support Serge Semin
2020-05-21 0:34 ` [PATCH v3 04/14] mips: Add MIPS Warrior P5600 support Serge Semin
2020-05-21 0:34 ` [PATCH v3 05/14] mips: Fix cpu_has_mips64r1/2 activation for MIPS32 CPUs Serge Semin
2020-05-21 0:34 ` [PATCH v3 06/14] mips: Add CP0 Write Merge config support Serge Semin
2020-05-21 0:34 ` [PATCH v3 07/14] mips: Add CONFIG/CONFIG6/Cause reg fields macro Serge Semin
2020-05-21 0:34 ` Serge Semin [this message]
2020-05-21 7:11 ` [PATCH v3 08/14] mips: MAAR: Use more precise address mask Thomas Bogendoerfer
2020-05-21 0:34 ` [PATCH v3 09/14] mips: Add CPS_NS16550_WIDTH config Serge Semin
2020-05-21 0:34 ` [PATCH v3 10/14] mips: cdmm: Add mti,mips-cdmm dtb node support Serge Semin
2020-05-21 0:34 ` [PATCH v3 11/14] bus: cdmm: Add MIPS R5 arch support Serge Semin
2020-05-21 10:25 ` Sergei Shtylyov
2020-05-21 12:58 ` Serge Semin
2020-05-21 15:44 ` Sergei Shtylyov
2020-05-21 0:34 ` [PATCH v3 12/14] mips: Add udelay lpj numbers adjustment Serge Semin
2020-05-21 0:34 ` [PATCH v3 13/14] mips: csrc-r4k: Mark R4K timer as unstable if CPU freq changes Serge Semin
2020-05-21 0:34 ` [PATCH v3 14/14] mips: cevt-r4k: Update the r4k-clockevent frequency in sync with CPU Serge Semin
2020-05-21 0:42 ` [PATCH v3 00/14] mips: Prepare MIPS-arch code for Baikal-T1 SoC support Serge Semin
2020-05-21 7:14 ` Thomas Bogendoerfer
2020-05-21 7:30 ` Arnd Bergmann
2020-05-21 13:48 ` Serge Semin
2020-05-21 13:50 ` Serge Semin
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