From: Apurva Nandan <a-nandan@ti.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Mark Brown <broonie@kernel.org>, Apurva Nandan <a-nandan@ti.com>,
Patrice Chotard <patrice.chotard@foss.st.com>,
Christophe Kerello <christophe.kerello@foss.st.com>,
Boris Brezillon <boris.brezillon@collabora.com>,
Daniel Palmer <daniel@0x0f.com>,
Alexander Lobakin <alobakin@pm.me>,
<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<linux-spi@vger.kernel.org>
Cc: <p.yadav@ti.com>
Subject: [PATCH v3 01/17] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase
Date: Sat, 1 Jan 2022 13:12:34 +0530 [thread overview]
Message-ID: <20220101074250.14443-2-a-nandan@ti.com> (raw)
In-Reply-To: <20220101074250.14443-1-a-nandan@ti.com>
Setting dtr field of spi_mem_op is useful when creating templates
for DTR ops in spinand.h. Also, 2 bytes cmd phases are required when
operating in Octal DTR SPI mode.
Create new templates for dtr mode cmd, address, dummy and data phase
in spi_mem_op, which set the dtr field to 1 and also allow passing
the nbytes for the cmd phase.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
---
include/linux/spi/spi-mem.h | 41 +++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index 85e2ff7b840d..682378a9c600 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -20,6 +20,14 @@
.nbytes = 1, \
}
+#define SPI_MEM_OP_CMD_DTR(__nbytes, __opcode, __buswidth) \
+ { \
+ .nbytes = __nbytes, \
+ .opcode = __opcode, \
+ .buswidth = __buswidth, \
+ .dtr = 1, \
+ }
+
#define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \
{ \
.nbytes = __nbytes, \
@@ -27,6 +35,14 @@
.buswidth = __buswidth, \
}
+#define SPI_MEM_OP_ADDR_DTR(__nbytes, __val, __buswidth) \
+ { \
+ .nbytes = __nbytes, \
+ .val = __val, \
+ .buswidth = __buswidth, \
+ .dtr = 1, \
+ }
+
#define SPI_MEM_OP_NO_ADDR { }
#define SPI_MEM_OP_DUMMY(__nbytes, __buswidth) \
@@ -35,6 +51,13 @@
.buswidth = __buswidth, \
}
+#define SPI_MEM_OP_DUMMY_DTR(__nbytes, __buswidth) \
+ { \
+ .nbytes = __nbytes, \
+ .buswidth = __buswidth, \
+ .dtr = 1, \
+ }
+
#define SPI_MEM_OP_NO_DUMMY { }
#define SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth) \
@@ -45,6 +68,15 @@
.buswidth = __buswidth, \
}
+#define SPI_MEM_OP_DATA_IN_DTR(__nbytes, __buf, __buswidth) \
+ { \
+ .dir = SPI_MEM_DATA_IN, \
+ .nbytes = __nbytes, \
+ .buf.in = __buf, \
+ .buswidth = __buswidth, \
+ .dtr = 1, \
+ }
+
#define SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth) \
{ \
.dir = SPI_MEM_DATA_OUT, \
@@ -53,6 +85,15 @@
.buswidth = __buswidth, \
}
+#define SPI_MEM_OP_DATA_OUT_DTR(__nbytes, __buf, __buswidth) \
+ { \
+ .dir = SPI_MEM_DATA_OUT, \
+ .nbytes = __nbytes, \
+ .buf.out = __buf, \
+ .buswidth = __buswidth, \
+ .dtr = 1, \
+ }
+
#define SPI_MEM_OP_NO_DATA { }
/**
--
2.25.1
next prev parent reply other threads:[~2022-01-01 7:43 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-01 7:42 [PATCH v3 00/17] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Apurva Nandan
2022-01-01 7:42 ` Apurva Nandan [this message]
2022-01-04 14:52 ` [PATCH v3 01/17] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Mark Brown
2022-01-04 15:31 ` Boris Brezillon
2022-01-05 5:50 ` Pratyush Yadav
2022-01-05 7:36 ` Boris Brezillon
2022-01-05 8:24 ` Tudor.Ambarus
2022-01-01 7:42 ` [PATCH v3 02/17] mtd: spinand: Define macros for Octal DTR ops Apurva Nandan
2022-01-01 7:42 ` [PATCH v3 03/17] mtd: spinand: Add enum spinand_protocol to indicate current SPI IO mode Apurva Nandan
2022-01-03 10:05 ` Boris Brezillon
2022-01-01 7:42 ` [PATCH v3 04/17] mtd: spinand: Rename 'op_templates' to 'data_ops' Apurva Nandan
2022-01-03 9:48 ` Boris Brezillon
2022-01-01 7:42 ` [PATCH v3 05/17] mtd: spinand: Define ctrl_ops for non-page read/write op templates Apurva Nandan
2022-01-03 10:01 ` Boris Brezillon
2022-01-03 10:36 ` Boris Brezillon
2022-02-15 15:33 ` Apurva Nandan
2022-02-15 17:37 ` Boris Brezillon
2022-03-02 15:30 ` Apurva Nandan
2022-03-02 20:05 ` Boris Brezillon
2022-03-10 7:57 ` Apurva Nandan
2022-03-10 8:40 ` Boris Brezillon
2022-03-14 11:47 ` Apurva Nandan
2022-01-01 7:42 ` [PATCH v3 06/17] mtd: spinand: Define default ctrl_ops in the core Apurva Nandan
2022-01-01 7:42 ` [PATCH v3 07/17] mtd: spinand: Switch from op macros usage to 'ctrl_ops' " Apurva Nandan
2022-01-01 7:42 ` [PATCH v3 08/17] mtd: spinand: Add support for manufacturer-based ctrl_ops variations Apurva Nandan
2022-01-01 7:42 ` [PATCH v3 09/17] mtd: spinand: Add change_mode() in manufacturer_ops Apurva Nandan
2022-01-05 9:52 ` Boris Brezillon
2022-01-01 7:42 ` [PATCH v3 10/17] mtd: spinand: Add pointer to probed flash's spinand_info Apurva Nandan
2022-01-01 7:42 ` [PATCH v3 11/17] mtd: spinand: Allow enabling/disabling Octal DTR mode in the core Apurva Nandan
2022-01-03 10:14 ` Boris Brezillon
2022-01-01 7:42 ` [PATCH v3 12/17] mtd: spinand: Add mtd_suspend() to disable Octal DTR mode at suspend Apurva Nandan
2022-01-03 10:17 ` Boris Brezillon
2022-01-01 7:42 ` [PATCH v3 13/17] mtd: spinand: winbond: Add support for write volatile configuration register op Apurva Nandan
2022-01-01 7:42 ` [PATCH v3 14/17] mtd: spinand: winbond: Add octal_dtr_enable/disable() in manufacturer_ops Apurva Nandan
2022-01-01 7:42 ` [PATCH v3 15/17] mtd: spianand: winbond: Add change_mode() manufacturer_ops Apurva Nandan
2022-01-03 10:27 ` Boris Brezillon
2022-01-01 7:42 ` [PATCH v3 16/17] mtd: spinand: winbond: Rename cache op_variants struct variable Apurva Nandan
2022-01-01 7:42 ` [PATCH v3 17/17] mtd: spinand: winbond: Add support for Winbond W35N01JW SPI NAND flash Apurva Nandan
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