[PATCH 0/1] coresight: no-op refactor to make INSTP0 check more idiomatic

[PATCH 0/1] coresight: no-op refactor to make INSTP0 check more idiomatic

[James Clark]

In preparation for the bigger register refactor, simplify one of the
accesses otherwise it looked even more obfuscated after the refactor.

This can't be included in the main set because it causes a small change
in the binary, although functionally this refactor is also a no-op.

Applies to coresight/next 30d1f1c71b

James Clark (1):
  coresight: no-op refactor to make INSTP0 check more idiomatic

 drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.28.0

[PATCH 1/1] coresight: no-op refactor to make INSTP0 check more idiomatic

[James Clark]

The spec says this:

  P0 tracing support field. The permitted values are:
      0b00  Tracing of load and store instructions as P0 elements is not
            supported.
      0b11  Tracing of load and store instructions as P0 elements is
            supported, so TRCCONFIGR.INSTP0 is supported.

            All other values are reserved.

The value we are looking for is 0b11 so simplify this. The double read
and && was a bit obfuscated.

Suggested-by: Suzuki Poulose <suzuki.poulose@arm.com>
Signed-off-by: James Clark <james.clark@arm.com>
---
 drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index bf18128cf5de..e2eebd865241 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -1091,7 +1091,7 @@ static void etm4_init_arch_data(void *info)
 	etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
 
 	/* INSTP0, bits[2:1] P0 tracing support field */
-	if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
+	if (BMVAL(etmidr0, 1, 2) == 0b11)
 		drvdata->instrp0 = true;
 	else
 		drvdata->instrp0 = false;
-- 
2.28.0

Re: [PATCH 1/1] coresight: no-op refactor to make INSTP0 check more idiomatic

[Suzuki K Poulose]

On 03/02/2022 11:53, James Clark wrote:
> The spec says this:
> 
>    P0 tracing support field. The permitted values are:
>        0b00  Tracing of load and store instructions as P0 elements is not
>              supported.
>        0b11  Tracing of load and store instructions as P0 elements is
>              supported, so TRCCONFIGR.INSTP0 is supported.
> 
>              All other values are reserved.
> 
> The value we are looking for is 0b11 so simplify this. The double read
> and && was a bit obfuscated.
> 
> Suggested-by: Suzuki Poulose <suzuki.poulose@arm.com>
> Signed-off-by: James Clark <james.clark@arm.com>

Thanks, Queued.

Cheers
Suzuki