From: Tianfei Zhang <tianfei.zhang@intel.com>
To: hao.wu@intel.com, trix@redhat.com, mdf@kernel.org,
yilun.xu@intel.com, linux-fpga@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
rdunlap@infradead.org
Cc: corbet@lwn.net, Matthew Gerlach <matthew.gerlach@linux.intel.com>,
Tianfei Zhang <tianfei.zhang@intel.com>
Subject: [PATCH v6 5/6] fpga: dfl: support PF/VF starting with DFH
Date: Wed, 16 Mar 2022 03:08:13 -0400 [thread overview]
Message-ID: <20220316070814.1916017-6-tianfei.zhang@intel.com> (raw)
In-Reply-To: <20220316070814.1916017-1-tianfei.zhang@intel.com>
From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
In OFS, it allows several PFs and VFs in static region or PR region.
Those PFs and VFs managed by DFL or a specific device, like virtio-net
device. Those PFs and VFs which managed by DFL can start with DFH, and
leverage VFIO to expose to an application or assign to a VM.
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
---
drivers/fpga/dfl-pci.c | 2 ++
drivers/fpga/dfl.c | 22 +++++++++++++---------
drivers/fpga/dfl.h | 7 +++++++
3 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
index 2e9abeca3625..7d8b53330152 100644
--- a/drivers/fpga/dfl-pci.c
+++ b/drivers/fpga/dfl-pci.c
@@ -275,6 +275,8 @@ static int find_dfls_by_default(struct pci_dev *pcidev,
len = pci_resource_len(pcidev, 0);
dfl_fpga_enum_info_add_dfl(info, start, len);
+ } else if (dfl_feature_is_afu(base)) {
+ dev_info(&pcidev->dev, "find AFU\n");
} else {
ret = -ENODEV;
}
diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
index 71e0725b6be0..db676f7482ec 100644
--- a/drivers/fpga/dfl.c
+++ b/drivers/fpga/dfl.c
@@ -900,9 +900,11 @@ static void build_info_free(struct build_feature_devs_info *binfo)
dfl_id_free(feature_dev_id_type(binfo->feature_dev),
binfo->feature_dev->id);
- list_for_each_entry_safe(finfo, p, &binfo->sub_features, node) {
- list_del(&finfo->node);
- kfree(finfo);
+ if (!list_empty(&binfo->sub_features)) {
+ list_for_each_entry_safe(finfo, p, &binfo->sub_features, node) {
+ list_del(&finfo->node);
+ kfree(finfo);
+ }
}
}
@@ -1444,12 +1446,14 @@ dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info)
* start enumeration for all feature devices based on Device Feature
* Lists.
*/
- list_for_each_entry(dfl, &info->dfls, node) {
- ret = parse_feature_list(binfo, dfl->start, dfl->len);
- if (ret) {
- remove_feature_devs(cdev);
- build_info_free(binfo);
- goto unregister_region_exit;
+ if (!list_empty(&info->dfls)) {
+ list_for_each_entry(dfl, &info->dfls, node) {
+ ret = parse_feature_list(binfo, dfl->start, dfl->len);
+ if (ret) {
+ remove_feature_devs(cdev);
+ build_info_free(binfo);
+ goto unregister_region_exit;
+ }
}
}
diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
index 83c2c50975e5..08edaeeb7f80 100644
--- a/drivers/fpga/dfl.h
+++ b/drivers/fpga/dfl.h
@@ -421,6 +421,13 @@ static inline bool dfl_feature_is_port(void __iomem *base)
(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
}
+static inline bool dfl_feature_is_afu(void __iomem *base)
+{
+ u64 v = readq(base + DFH);
+
+ return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_AFU);
+}
+
static inline u8 dfl_feature_revision(void __iomem *base)
{
return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH));
--
2.26.2
next prev parent reply other threads:[~2022-03-16 7:12 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-16 7:08 [PATCH v6 0/6] Add OFS support for DFL driver Tianfei Zhang
2022-03-16 7:08 ` [PATCH v6 1/6] fpga: dfl: Allow ports without local bar space Tianfei Zhang
2022-03-17 2:04 ` Wu, Hao
2022-03-17 7:34 ` Zhang, Tianfei
2022-03-17 8:17 ` Wu, Hao
2022-03-17 8:32 ` Zhang, Tianfei
2022-03-16 7:08 ` [PATCH v6 2/6] fpga: dfl: tracking port conntected with AFU Tianfei Zhang
2022-03-17 8:25 ` Wu, Hao
2022-03-17 8:57 ` Zhang, Tianfei
2022-03-16 7:08 ` [PATCH v6 3/6] fpga: dfl: check released_port_num and num_vfs for legacy model Tianfei Zhang
2022-03-17 8:49 ` Wu, Hao
2022-03-17 9:02 ` Zhang, Tianfei
2022-03-16 7:08 ` [PATCH v6 4/6] fpga: dfl: configure port access mode for afu connected with port Tianfei Zhang
2022-03-16 7:08 ` Tianfei Zhang [this message]
2022-03-16 7:08 ` [PATCH v6 6/6] Documentation: fpga: dfl: add description of OFS Tianfei Zhang
2022-03-17 8:36 ` Wu, Hao
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