RE: [PATCH v6 1/6] fpga: dfl: Allow ports without local bar space.

["Wu, Hao" <hao.wu@intel.com>]

> -----Original Message-----
> From: Zhang, Tianfei <tianfei.zhang@intel.com>
> Sent: Wednesday, March 16, 2022 3:08 PM
> To: Wu, Hao <hao.wu@intel.com>; trix@redhat.com; mdf@kernel.org; Xu, Yilun
> <yilun.xu@intel.com>; linux-fpga@vger.kernel.org; linux-doc@vger.kernel.org;
> linux-kernel@vger.kernel.org; rdunlap@infradead.org
> Cc: corbet@lwn.net; Matthew Gerlach <matthew.gerlach@linux.intel.com>;
> Zhang, Tianfei <tianfei.zhang@intel.com>
> Subject: [PATCH v6 1/6] fpga: dfl: Allow ports without local bar space.
> 
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> 
> In OFS, each PR slot (AFU) has one port device which include Port
> control, Port user clock control and Port errors. In legacy model,
> the AFU MMIO space was connected with Port device, so from port
> device point of view, there is a bar space associated with this
> port device. But in "Multiple VFs per PR slot" model, the AFU MMIO
> space was not connected with Port device. The BarID (3bits field) in
> PORTn_OFFSET register indicates which PCI bar space associated with
> this port device, the value 0b111 (FME_HDR_NO_PORT_BAR) means that
> no PCI bar for this port device.

The commit message is not matching the change, it's not related to AFU...

Current usage (FME DFL and PORT DFL are not linked together)

FME DFL 
PORT DFL (located by FME's PORTn_OFFSET register, BAR + offset)

Your proposed new usage is (FME DFL and PORT DFL are linked together)

FME DFL -> PORT DFL
So FME's PORTn_OFFSET can be marked, then driver could skip it.

Is my understanding correct? If yes, please update your title and commit
message, and add some comments in code as well.

Again, the change you did in dfl core code, is not only impacting your
OFS device, but also future DFL devices, it's an extension to DFL.

Thanks
Hao

> 
> ---
> v3: add PCI bar number checking with PCI_STD_NUM_BARS.
> v2: use FME_HDR_NO_PORT_BAR instead of PCI_STD_NUM_BARS.
> 
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
> ---
>  drivers/fpga/dfl-pci.c | 7 +++++++
>  drivers/fpga/dfl.h     | 1 +
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
> index 4d68719e608f..2e9abeca3625 100644
> --- a/drivers/fpga/dfl-pci.c
> +++ b/drivers/fpga/dfl-pci.c
> @@ -258,6 +258,13 @@ static int find_dfls_by_default(struct pci_dev *pcidev,
>  			 */
>  			bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
>  			offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
> +			if (bar >= PCI_STD_NUM_BARS ||
> +			    bar == FME_HDR_NO_PORT_BAR) {
> +				dev_dbg(&pcidev->dev, "skipping port without
> local BAR space %d\n",
> +					bar);
> +				continue;
> +			}
> +
>  			start = pci_resource_start(pcidev, bar) + offset;
>  			len = pci_resource_len(pcidev, bar) - offset;
> 
> diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
> index 53572c7aced0..1fd493e82dd8 100644
> --- a/drivers/fpga/dfl.h
> +++ b/drivers/fpga/dfl.h
> @@ -91,6 +91,7 @@
>  #define FME_HDR_PORT_OFST(n)	(0x38 + ((n) * 0x8))
>  #define FME_HDR_BITSTREAM_ID	0x60
>  #define FME_HDR_BITSTREAM_MD	0x68
> +#define FME_HDR_NO_PORT_BAR	7
> 
>  /* FME Fab Capability Register Bitfield */
>  #define FME_CAP_FABRIC_VERID	GENMASK_ULL(7, 0)	/* Fabric
> version ID */
> --
> 2.26.2