From: Sean Christopherson <seanjc@google.com>
To: Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
Alejandro Jimenez <alejandro.j.jimenez@oracle.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
Maxim Levitsky <mlevitsk@redhat.com>,
Li RongQing <lirongqing@baidu.com>
Subject: [PATCH v3 17/28] KVM: x86: Skip redundant x2APIC logical mode optimized cluster setup
Date: Tue, 20 Sep 2022 23:31:23 +0000 [thread overview]
Message-ID: <20220920233134.940511-18-seanjc@google.com> (raw)
In-Reply-To: <20220920233134.940511-1-seanjc@google.com>
Skip the optimized cluster[] setup for x2APIC logical mode, as KVM reuses
the optimized map's phys_map[] and doesn't actually need to insert the
target apic into the cluster[]. The LDR is derived from the x2APIC ID,
and both are read-only in KVM, thus the vCPU's cluster[ldr] is guaranteed
to be the same entry as the vCPU's phys_map[x2apic_id] entry.
Skipping the unnecessary setup will allow a future fix for aliased xAPIC
logical IDs to simply require that cluster[ldr] is non-NULL, i.e. won't
have to special case x2APIC.
Alternatively, the future check could allow "cluster[ldr] == apic", but
that ends up being terribly confusing because cluster[ldr] is only set
at the very end, i.e. it's only possible due to x2APIC's shenanigans.
Another alternative would be to send x2APIC down a separate path _after_
the calculation and then assert that all of the above, but the resulting
code is rather messy, and it's arguably unnecessary since asserting that
the actual LDR matches the expected LDR means that simply testing that
interrupts are delivered correctly provides the same guarantees.
Reported-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
arch/x86/kvm/lapic.c | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 84b7a1c1834d..7a39d7be4cc9 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -166,6 +166,11 @@ static bool kvm_use_posted_timer_interrupt(struct kvm_vcpu *vcpu)
return kvm_can_post_timer_interrupt(vcpu) && vcpu->mode == IN_GUEST_MODE;
}
+static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
+{
+ return ((id >> 4) << 16) | (1 << (id & 0xf));
+}
+
static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
switch (map->logical_mode) {
@@ -315,6 +320,18 @@ void kvm_recalculate_apic_map(struct kvm *kvm)
}
new->logical_mode = logical_mode;
+ /*
+ * In x2APIC mode, the LDR is read-only and derived directly
+ * from the x2APIC ID, thus is guaranteed to be addressable.
+ * KVM reuses kvm_apic_map.phys_map to optimize logical mode
+ * x2APIC interrupts by reversing the LDR calculation to get
+ * cluster of APICs, i.e. no additional work is required.
+ */
+ if (apic_x2apic_mode(apic)) {
+ WARN_ON_ONCE(ldr != kvm_apic_calc_x2apic_ldr(x2apic_id));
+ continue;
+ }
+
if (WARN_ON_ONCE(!kvm_apic_map_get_logical_dest(new, ldr,
&cluster, &mask))) {
new->logical_mode = KVM_APIC_MODE_MAP_DISABLED;
@@ -381,11 +398,6 @@ static inline void kvm_apic_set_dfr(struct kvm_lapic *apic, u32 val)
atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
}
-static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
-{
- return ((id >> 4) << 16) | (1 << (id & 0xf));
-}
-
static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
{
u32 ldr = kvm_apic_calc_x2apic_ldr(id);
--
2.37.3.968.ga6b4b080e4-goog
next prev parent reply other threads:[~2022-09-20 23:33 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-20 23:31 [PATCH v3 00/28] KVM: x86: AVIC and local APIC fixes+cleanups Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 01/28] KVM: x86: Blindly get current x2APIC reg value on "nodecode write" traps Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 02/28] KVM: x86: Purge "highest ISR" cache when updating APICv state Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 03/28] KVM: SVM: Flush the "current" TLB when activating AVIC Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 04/28] KVM: SVM: Process ICR on AVIC IPI delivery failure due to invalid target Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 05/28] KVM: x86: Don't inhibit APICv/AVIC if xAPIC ID mismatch is due to 32-bit ID Sean Christopherson
2022-09-28 3:15 ` Alejandro Jimenez
2022-09-28 5:55 ` Maxim Levitsky
2022-09-28 16:51 ` Sean Christopherson
2022-09-28 17:51 ` Maxim Levitsky
2022-09-28 18:03 ` Sean Christopherson
2022-09-28 18:16 ` Maxim Levitsky
2022-09-28 20:44 ` Sean Christopherson
2022-09-28 20:50 ` Alejandro Jimenez
2022-09-20 23:31 ` [PATCH v3 06/28] KVM: x86: Move APIC access page helper to common x86 code Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 07/28] KVM: x86: Inhibit APIC memslot if x2APIC and AVIC are enabled Sean Christopherson
2022-09-23 10:27 ` Maxim Levitsky
2022-09-26 17:00 ` Sean Christopherson
2022-09-28 6:21 ` Maxim Levitsky
2022-09-28 16:33 ` Sean Christopherson
2022-09-28 17:40 ` Maxim Levitsky
2022-09-28 22:35 ` Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 08/28] KVM: SVM: Don't put/load AVIC when setting virtual APIC mode Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 09/28] KVM: SVM: Replace "avic_mode" enum with "x2avic_enabled" boolean Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 10/28] KVM: SVM: Compute dest based on sender's x2APIC status for AVIC kick Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 11/28] KVM: SVM: Fix x2APIC Logical ID calculation for avic_kick_target_vcpus_fast Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 12/28] Revert "KVM: SVM: Use target APIC ID to complete x2AVIC IRQs when possible" Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 13/28] KVM: SVM: Document that vCPU ID == APIC ID in AVIC kick fastpatch Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 14/28] KVM: SVM: Add helper to perform final AVIC "kick" of single vCPU Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 15/28] KVM: x86: Explicitly skip optimized logical map setup if vCPU's LDR==0 Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 16/28] KVM: x86: Explicitly track all possibilities for APIC map's logical modes Sean Christopherson
2022-09-20 23:31 ` Sean Christopherson [this message]
2022-09-20 23:31 ` [PATCH v3 18/28] KVM: x86: Disable APIC logical map if logical ID covers multiple MDAs Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 19/28] KVM: x86: Disable APIC logical map if vCPUs are aliased in logical mode Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 20/28] KVM: x86: Honor architectural behavior for aliased 8-bit APIC IDs Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 21/28] KVM: x86: Inhibit APICv/AVIC if the optimized physical map is disabled Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 22/28] KVM: SVM: Inhibit AVIC if vCPUs are aliased in logical mode Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 23/28] KVM: SVM: Always update local APIC on writes to logical dest register Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 24/28] KVM: SVM: Update svm->ldr_reg cache even if LDR is "bad" Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 25/28] KVM: SVM: Require logical ID to be power-of-2 for AVIC entry Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 26/28] KVM: SVM: Handle multiple logical targets in AVIC kick fastpath Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 27/28] KVM: SVM: Ignore writes to Remote Read Data on AVIC write traps Sean Christopherson
2022-09-20 23:31 ` [PATCH v3 28/28] Revert "KVM: SVM: Do not throw warning when calling avic_vcpu_load on a running vcpu" Sean Christopherson
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