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From: "Clément Léger" <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: "Clément Léger" <cleger@rivosinc.com>,
	"Stafford Horne" <shorne@gmail.com>,
	"Brian Cain" <bcain@quicinc.com>,
	"Kefeng Wang" <wangkefeng.wang@huawei.com>,
	"Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>,
	"Michael Ellerman" <mpe@ellerman.id.au>,
	"Sunil V L" <sunilvl@ventanamicro.com>,
	"Anup Patel" <apatel@ventanamicro.com>,
	"Atish Patra" <atishp@rivosinc.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Heiko Stuebner" <heiko@sntech.de>, "Guo Ren" <guoren@kernel.org>,
	"Alexandre Ghiti" <alexghiti@rivosinc.com>,
	"Masahiro Yamada" <masahiroy@kernel.org>,
	"Xianting Tian" <xianting.tian@linux.alibaba.com>,
	"Sia Jee Heng" <jeeheng.sia@starfivetech.com>,
	"Li Zhengyu" <lizhengyu3@huawei.com>,
	"Jisheng Zhang" <jszhang@kernel.org>,
	"Gautham R. Shenoy" <gautham.shenoy@amd.com>,
	"Mark Rutland" <mark.rutland@arm.com>,
	"Peter Zijlstra" <peterz@infradead.org>,
	"Marc Zyngier" <maz@kernel.org>,
	"Björn Töpel" <bjorn@rivosinc.com>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>,
	"Evan Green" <evan@rivosinc.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [RFC V2 PATCH 1/9] riscv: remove unused functions in traps_misaligned.c
Date: Tue,  4 Jul 2023 16:09:16 +0200	[thread overview]
Message-ID: <20230704140924.315594-2-cleger@rivosinc.com> (raw)
In-Reply-To: <20230704140924.315594-1-cleger@rivosinc.com>

Replace macros by the only two function calls that are done from this
file, store_u8() and load_u8().

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/kernel/traps_misaligned.c | 46 +++++-----------------------
 1 file changed, 7 insertions(+), 39 deletions(-)

diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 378f5b151443..e7bfb33089c1 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -151,51 +151,19 @@
 #define PRECISION_S 0
 #define PRECISION_D 1
 
-#define DECLARE_UNPRIVILEGED_LOAD_FUNCTION(type, insn)			\
-static inline type load_##type(const type *addr)			\
-{									\
-	type val;							\
-	asm (#insn " %0, %1"						\
-	: "=&r" (val) : "m" (*addr));					\
-	return val;							\
-}
+static inline u8 load_u8(const u8 *addr)
+{
+	u8 val;
 
-#define DECLARE_UNPRIVILEGED_STORE_FUNCTION(type, insn)			\
-static inline void store_##type(type *addr, type val)			\
-{									\
-	asm volatile (#insn " %0, %1\n"					\
-	: : "r" (val), "m" (*addr));					\
-}
+	asm volatile("lbu %0, %1" : "=&r" (val) : "m" (*addr));
 
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u8, lbu)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u16, lhu)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s8, lb)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s16, lh)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s32, lw)
-DECLARE_UNPRIVILEGED_STORE_FUNCTION(u8, sb)
-DECLARE_UNPRIVILEGED_STORE_FUNCTION(u16, sh)
-DECLARE_UNPRIVILEGED_STORE_FUNCTION(u32, sw)
-#if defined(CONFIG_64BIT)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lwu)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u64, ld)
-DECLARE_UNPRIVILEGED_STORE_FUNCTION(u64, sd)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld)
-#else
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw)
-DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw)
-
-static inline u64 load_u64(const u64 *addr)
-{
-	return load_u32((u32 *)addr)
-		+ ((u64)load_u32((u32 *)addr + 1) << 32);
+	return val;
 }
 
-static inline void store_u64(u64 *addr, u64 val)
+static inline void store_u8(u8 *addr, u8 val)
 {
-	store_u32((u32 *)addr, val);
-	store_u32((u32 *)addr + 1, val >> 32);
+	asm volatile ("sb %0, %1\n" : : "r" (val), "m" (*addr));
 }
-#endif
 
 static inline ulong get_insn(ulong mepc)
 {
-- 
2.40.1


  reply	other threads:[~2023-07-04 14:10 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-04 14:09 [RFC V2 PATCH 0/9] Add support to handle misaligned accesses in S-mode Clément Léger
2023-07-04 14:09 ` Clément Léger [this message]
2023-07-04 14:09 ` [RFC V2 PATCH 2/9] riscv: avoid missing prototypes warning Clément Léger
2023-07-08 19:34   ` Stafford Horne
2023-07-04 14:09 ` [RFC V2 PATCH 3/9] riscv: add support for misaligned handling in S-mode Clément Léger
2023-07-08 20:08   ` Stafford Horne
2023-07-04 14:09 ` [RFC V2 PATCH 4/9] riscv: report perf event for misaligned fault Clément Léger
2023-07-04 14:09 ` [RFC V2 PATCH 5/9] riscv: add support for sysctl unaligned_enabled control Clément Léger
2023-07-04 14:09 ` [RFC V2 PATCH 6/9] riscv: add support for SBI misalignment trap delegation Clément Léger
2023-07-04 14:09 ` [RFC V2 PATCH 7/9] riscv: report misaligned accesses emulation to hwprobe Clément Léger
2023-07-04 14:09 ` [RFC V2 PATCH 8/9] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN Clément Léger
2023-07-04 14:09 ` [RFC V2 PATCH 9/9] riscv: add floating point insn support to misaligned access emulation Clément Léger

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