From: "Clément Léger" <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: "Clément Léger" <cleger@rivosinc.com>,
"Stafford Horne" <shorne@gmail.com>,
"Brian Cain" <bcain@quicinc.com>,
"Kefeng Wang" <wangkefeng.wang@huawei.com>,
"Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>,
"Michael Ellerman" <mpe@ellerman.id.au>,
"Sunil V L" <sunilvl@ventanamicro.com>,
"Anup Patel" <apatel@ventanamicro.com>,
"Atish Patra" <atishp@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Heiko Stuebner" <heiko@sntech.de>, "Guo Ren" <guoren@kernel.org>,
"Alexandre Ghiti" <alexghiti@rivosinc.com>,
"Masahiro Yamada" <masahiroy@kernel.org>,
"Xianting Tian" <xianting.tian@linux.alibaba.com>,
"Sia Jee Heng" <jeeheng.sia@starfivetech.com>,
"Li Zhengyu" <lizhengyu3@huawei.com>,
"Jisheng Zhang" <jszhang@kernel.org>,
"Gautham R. Shenoy" <gautham.shenoy@amd.com>,
"Mark Rutland" <mark.rutland@arm.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Marc Zyngier" <maz@kernel.org>,
"Björn Töpel" <bjorn@rivosinc.com>,
"Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>,
"Evan Green" <evan@rivosinc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [RFC V2 PATCH 6/9] riscv: add support for SBI misalignment trap delegation
Date: Tue, 4 Jul 2023 16:09:21 +0200 [thread overview]
Message-ID: <20230704140924.315594-7-cleger@rivosinc.com> (raw)
In-Reply-To: <20230704140924.315594-1-cleger@rivosinc.com>
Add support for misalignment trap delegation by setting it with
SBI_EXT_FW_FEATURE SBI extension. This extension allows to control SBI
behavior by requesting to set them to specific value. In order to
implement prctl(PR_SET_UNALIGN, PR_UNALIGN_SIGBUS) behavior properly, we
need to let the kernel handle the misalignment error by itself.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
arch/riscv/include/asm/sbi.h | 11 +++++++++++
arch/riscv/kernel/sbi.c | 21 +++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 5b4a1bf5f439..c1b74c7d0d56 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -30,6 +30,7 @@ enum sbi_ext_id {
SBI_EXT_HSM = 0x48534D,
SBI_EXT_SRST = 0x53525354,
SBI_EXT_PMU = 0x504D55,
+ SBI_EXT_FW_FEATURE = 0x46574654,
/* Experimentals extensions must lie within this range */
SBI_EXT_EXPERIMENTAL_START = 0x08000000,
@@ -236,6 +237,16 @@ enum sbi_pmu_ctr_type {
/* Flags defined for counter stop function */
#define SBI_PMU_STOP_FLAG_RESET (1 << 0)
+/* SBI function IDs for FW feature extension */
+#define SBI_EXT_FW_FEATURE_SET 0x0
+#define SBI_EXT_FW_FEATURE_GET 0x1
+
+enum sbi_fw_features_t {
+ SBI_FW_FEATURE_MISALIGNED_DELEG = 0,
+
+ SBI_FW_FEATURE_MAX,
+};
+
#define SBI_SPEC_VERSION_DEFAULT 0x1
#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index c672c8ba9a2a..3be48791455a 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -494,6 +494,16 @@ int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask,
}
EXPORT_SYMBOL(sbi_remote_hfence_vvma_asid);
+static int sbi_fw_feature_set(enum sbi_fw_features_t feature, bool set)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_FW_FEATURE, SBI_EXT_FW_FEATURE_SET, feature,
+ set, 0, 0, 0, 0);
+
+ return sbi_err_map_linux_errno(ret.error);
+}
+
static void sbi_srst_reset(unsigned long type, unsigned long reason)
{
sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason,
@@ -624,6 +634,17 @@ void __init sbi_init(void)
sbi_srst_reboot_nb.priority = 192;
register_restart_handler(&sbi_srst_reboot_nb);
}
+ /*
+ * TODO: this will likely need to be updated when SBI extension
+ * is ratified
+ */
+ if ((sbi_spec_version >= sbi_mk_version(1, 0)) &&
+ (sbi_probe_extension(SBI_EXT_FW_FEATURE) > 0)) {
+ pr_info("SBI FW_FEATURE extension detected\n");
+ /* Request misaligned handling delegation */
+ sbi_fw_feature_set(SBI_FW_FEATURE_MISALIGNED_DELEG,
+ true);
+ }
} else {
__sbi_set_timer = __sbi_set_timer_v01;
__sbi_send_ipi = __sbi_send_ipi_v01;
--
2.40.1
next prev parent reply other threads:[~2023-07-04 14:11 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 14:09 [RFC V2 PATCH 0/9] Add support to handle misaligned accesses in S-mode Clément Léger
2023-07-04 14:09 ` [RFC V2 PATCH 1/9] riscv: remove unused functions in traps_misaligned.c Clément Léger
2023-07-04 14:09 ` [RFC V2 PATCH 2/9] riscv: avoid missing prototypes warning Clément Léger
2023-07-08 19:34 ` Stafford Horne
2023-07-04 14:09 ` [RFC V2 PATCH 3/9] riscv: add support for misaligned handling in S-mode Clément Léger
2023-07-08 20:08 ` Stafford Horne
2023-07-04 14:09 ` [RFC V2 PATCH 4/9] riscv: report perf event for misaligned fault Clément Léger
2023-07-04 14:09 ` [RFC V2 PATCH 5/9] riscv: add support for sysctl unaligned_enabled control Clément Léger
2023-07-04 14:09 ` Clément Léger [this message]
2023-07-04 14:09 ` [RFC V2 PATCH 7/9] riscv: report misaligned accesses emulation to hwprobe Clément Léger
2023-07-04 14:09 ` [RFC V2 PATCH 8/9] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN Clément Léger
2023-07-04 14:09 ` [RFC V2 PATCH 9/9] riscv: add floating point insn support to misaligned access emulation Clément Léger
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