From: "Clément Léger" <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: "Clément Léger" <cleger@rivosinc.com>,
"Stafford Horne" <shorne@gmail.com>,
"Brian Cain" <bcain@quicinc.com>,
"Kefeng Wang" <wangkefeng.wang@huawei.com>,
"Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>,
"Michael Ellerman" <mpe@ellerman.id.au>,
"Sunil V L" <sunilvl@ventanamicro.com>,
"Anup Patel" <apatel@ventanamicro.com>,
"Atish Patra" <atishp@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Heiko Stuebner" <heiko@sntech.de>, "Guo Ren" <guoren@kernel.org>,
"Alexandre Ghiti" <alexghiti@rivosinc.com>,
"Masahiro Yamada" <masahiroy@kernel.org>,
"Xianting Tian" <xianting.tian@linux.alibaba.com>,
"Sia Jee Heng" <jeeheng.sia@starfivetech.com>,
"Li Zhengyu" <lizhengyu3@huawei.com>,
"Jisheng Zhang" <jszhang@kernel.org>,
"Gautham R. Shenoy" <gautham.shenoy@amd.com>,
"Mark Rutland" <mark.rutland@arm.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Marc Zyngier" <maz@kernel.org>,
"Björn Töpel" <bjorn@rivosinc.com>,
"Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>,
"Evan Green" <evan@rivosinc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [RFC V2 PATCH 2/9] riscv: avoid missing prototypes warning
Date: Tue, 4 Jul 2023 16:09:17 +0200 [thread overview]
Message-ID: <20230704140924.315594-3-cleger@rivosinc.com> (raw)
In-Reply-To: <20230704140924.315594-1-cleger@rivosinc.com>
Declare handle_misaligned_store/load() functions in entry-common.h and
include that file in traps_misaligned.c file to avoid warnings.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
arch/riscv/include/asm/entry-common.h | 3 +++
arch/riscv/kernel/traps.c | 2 --
arch/riscv/kernel/traps_misaligned.c | 1 +
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h
index 6e4dee49d84b..58e9e2976e1b 100644
--- a/arch/riscv/include/asm/entry-common.h
+++ b/arch/riscv/include/asm/entry-common.h
@@ -8,4 +8,7 @@
void handle_page_fault(struct pt_regs *regs);
void handle_break(struct pt_regs *regs);
+int handle_misaligned_load(struct pt_regs *regs);
+int handle_misaligned_store(struct pt_regs *regs);
+
#endif /* _ASM_RISCV_ENTRY_COMMON_H */
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index 8c258b78c925..7fcaf2fd27a1 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -155,8 +155,6 @@ DO_ERROR_INFO(do_trap_load_misaligned,
DO_ERROR_INFO(do_trap_store_misaligned,
SIGBUS, BUS_ADRALN, "Oops - store (or AMO) address misaligned");
#else
-int handle_misaligned_load(struct pt_regs *regs);
-int handle_misaligned_store(struct pt_regs *regs);
asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs)
{
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index e7bfb33089c1..0cccac4822a8 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -12,6 +12,7 @@
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/csr.h>
+#include <asm/entry-common.h>
#define INSN_MATCH_LB 0x3
#define INSN_MASK_LB 0x707f
--
2.40.1
next prev parent reply other threads:[~2023-07-04 14:10 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 14:09 [RFC V2 PATCH 0/9] Add support to handle misaligned accesses in S-mode Clément Léger
2023-07-04 14:09 ` [RFC V2 PATCH 1/9] riscv: remove unused functions in traps_misaligned.c Clément Léger
2023-07-04 14:09 ` Clément Léger [this message]
2023-07-08 19:34 ` [RFC V2 PATCH 2/9] riscv: avoid missing prototypes warning Stafford Horne
2023-07-04 14:09 ` [RFC V2 PATCH 3/9] riscv: add support for misaligned handling in S-mode Clément Léger
2023-07-08 20:08 ` Stafford Horne
2023-07-04 14:09 ` [RFC V2 PATCH 4/9] riscv: report perf event for misaligned fault Clément Léger
2023-07-04 14:09 ` [RFC V2 PATCH 5/9] riscv: add support for sysctl unaligned_enabled control Clément Léger
2023-07-04 14:09 ` [RFC V2 PATCH 6/9] riscv: add support for SBI misalignment trap delegation Clément Léger
2023-07-04 14:09 ` [RFC V2 PATCH 7/9] riscv: report misaligned accesses emulation to hwprobe Clément Léger
2023-07-04 14:09 ` [RFC V2 PATCH 8/9] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN Clément Léger
2023-07-04 14:09 ` [RFC V2 PATCH 9/9] riscv: add floating point insn support to misaligned access emulation Clément Léger
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