From: Mario Limonciello <mario.limonciello@amd.com>
To: "Borislav Petkov" <bp@alien8.de>,
"Hans de Goede" <hdegoede@redhat.com>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: <x86@kernel.org>, "Gautham R . Shenoy" <gautham.shenoy@amd.com>,
"Mario Limonciello" <mario.limonciello@amd.com>,
Perry Yuan <perry.yuan@amd.com>, <linux-kernel@vger.kernel.org>,
<linux-doc@vger.kernel.org>, <linux-pm@vger.kernel.org>,
<platform-driver-x86@vger.kernel.org>,
"Shyam Sundar S K" <Shyam-sundar.S-k@amd.com>
Subject: [PATCH v3 00/14] Add support for AMD hardware feedback interface
Date: Tue, 15 Oct 2024 16:36:31 -0500 [thread overview]
Message-ID: <20241015213645.1476-1-mario.limonciello@amd.com> (raw)
The AMD Heterogeneous core design and Hardware Feedback Interface (HFI)
provide behavioral classification and a dynamically updated ranking table
for the scheduler to use when choosing cores for tasks.
Threads are classified during runtime into enumerated classes.
Currently, the driver supports 3 classes (0 through 2). These classes
represent thread performance/power characteristics that may benefit from
special scheduling behaviors. The real-time thread classification is
consumed by the operating system and is used to inform the scheduler of
where the thread should be placed for optimal performance or energy efficiency.
The thread classification helps to select CPU from a ranking table that describes
an efficiency and performance ranking for each classification from two dimensions.
The ranking data provided by the ranking table are numbers ranging from 0 to 255,
where a higher performance value indicates higher performance capability and a higher
efficiency value indicates greater efficiency. All the CPU cores are ranked into
different class IDs. Within each class ranking, the cores may have different ranking
values. Therefore, picking from each classification ID will later allow the scheduler
to select the best core while threads are classified into the specified workload class.
This series was originally submitted by Perry Yuan [1] but he is now doing a different
role and he asked me to take over.
Link: https://lore.kernel.org/all/cover.1724748733.git.perry.yuan@amd.com/
On applicable hardware this series has between a 2% and 5% improvement across various
benchmarks.
There is however a cost associated with clearing history on the process context switch.
On average it increases the delay by 119ns, and also has a wider range in delays
(the standard deviation is 25% greater).
Although this series most prominently has changes to platform-x86 it is based
off of https://git.kernel.org/pub/scm/linux/kernel/git/superm1/linux.git/log/?h=linux-next
due to changes queued up for 6.13-rc1 that are dependencies.
---
v2->v3:
* Take into mailing list feedback for various patches (see patches for details)
* Add a patch to show the performance and efficiency rankings in debugfs
Mario Limonciello (4):
MAINTAINERS: Add maintainer entry for AMD Hardware Feedback Driver
cpufreq/amd-pstate: Disable preferred cores on designs with workload
classification
platform/x86/amd: hfi: Set ITMT priority from ranking data
platform/x86: hfi: Add debugfs support
Perry Yuan (10):
Documentation: x86: Add AMD Hardware Feedback Interface documentation
x86/cpufeatures: add X86_FEATURE_WORKLOAD_CLASS feature bit
x86/msr-index: define AMD heterogeneous CPU related MSR
platform/x86: hfi: Introduce AMD Hardware Feedback Interface Driver
platform/x86: hfi: parse CPU core ranking data from shared memory
platform/x86: hfi: init per-cpu scores for each class
platform/x86: hfi: add online and offline callback support
platform/x86: hfi: add power management callback
x86/cpu: Enable SD_ASYM_PACKING for DIE Domain on AMD Processors
x86/process: Clear hardware feedback history for AMD processors
Documentation/arch/x86/amd-hfi.rst | 115 ++++++
Documentation/arch/x86/index.rst | 1 +
MAINTAINERS | 9 +
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/include/asm/hreset.h | 6 +
arch/x86/include/asm/msr-index.h | 5 +
arch/x86/kernel/cpu/common.c | 15 +
arch/x86/kernel/cpu/scattered.c | 1 +
arch/x86/kernel/process_32.c | 3 +
arch/x86/kernel/process_64.c | 3 +
arch/x86/kernel/smpboot.c | 5 +-
drivers/cpufreq/amd-pstate.c | 6 +
drivers/platform/x86/amd/Kconfig | 1 +
drivers/platform/x86/amd/Makefile | 1 +
drivers/platform/x86/amd/hfi/Kconfig | 21 +
drivers/platform/x86/amd/hfi/Makefile | 7 +
drivers/platform/x86/amd/hfi/hfi.c | 552 ++++++++++++++++++++++++++
17 files changed, 750 insertions(+), 2 deletions(-)
create mode 100644 Documentation/arch/x86/amd-hfi.rst
create mode 100644 arch/x86/include/asm/hreset.h
create mode 100644 drivers/platform/x86/amd/hfi/Kconfig
create mode 100644 drivers/platform/x86/amd/hfi/Makefile
create mode 100644 drivers/platform/x86/amd/hfi/hfi.c
--
2.43.0
next reply other threads:[~2024-10-15 21:37 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-15 21:36 Mario Limonciello [this message]
2024-10-15 21:36 ` [PATCH v3 01/14] Documentation: x86: Add AMD Hardware Feedback Interface documentation Mario Limonciello
2024-10-15 21:36 ` [PATCH v3 02/14] MAINTAINERS: Add maintainer entry for AMD Hardware Feedback Driver Mario Limonciello
2024-10-15 21:36 ` [PATCH v3 03/14] x86/cpufeatures: add X86_FEATURE_WORKLOAD_CLASS feature bit Mario Limonciello
2024-10-17 4:47 ` Gautham R. Shenoy
2024-10-22 12:42 ` Borislav Petkov
2024-10-22 13:03 ` Mario Limonciello
2024-10-15 21:36 ` [PATCH v3 04/14] x86/msr-index: define AMD heterogeneous CPU related MSR Mario Limonciello
2024-10-17 4:48 ` Gautham R. Shenoy
2024-10-15 21:36 ` [PATCH v3 05/14] platform/x86: hfi: Introduce AMD Hardware Feedback Interface Driver Mario Limonciello
2024-10-17 6:07 ` Gautham R. Shenoy
2024-10-15 21:36 ` [PATCH v3 06/14] platform/x86: hfi: parse CPU core ranking data from shared memory Mario Limonciello
2024-10-15 21:36 ` [PATCH v3 07/14] platform/x86: hfi: init per-cpu scores for each class Mario Limonciello
2024-10-17 5:52 ` Gautham R. Shenoy
2024-10-15 21:36 ` [PATCH v3 08/14] platform/x86: hfi: add online and offline callback support Mario Limonciello
2024-10-16 12:42 ` Ilpo Järvinen
2024-10-15 21:36 ` [PATCH v3 09/14] platform/x86: hfi: add power management callback Mario Limonciello
2024-10-17 6:00 ` Gautham R. Shenoy
2024-10-17 19:27 ` Mario Limonciello
2024-10-15 21:36 ` [PATCH v3 10/14] x86/cpu: Enable SD_ASYM_PACKING for DIE Domain on AMD Processors Mario Limonciello
2024-10-17 6:06 ` Gautham R. Shenoy
2024-10-15 21:36 ` [PATCH v3 11/14] x86/process: Clear hardware feedback history for AMD processors Mario Limonciello
2024-10-15 21:36 ` [PATCH v3 12/14] cpufreq/amd-pstate: Disable preferred cores on designs with workload classification Mario Limonciello
2024-10-15 21:36 ` [PATCH v3 13/14] platform/x86/amd: hfi: Set ITMT priority from ranking data Mario Limonciello
2024-10-15 21:36 ` [PATCH v3 14/14] platform/x86: hfi: Add debugfs support Mario Limonciello
2024-10-16 12:38 ` Ilpo Järvinen
2024-10-16 16:09 ` Mario Limonciello
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20241015213645.1476-1-mario.limonciello@amd.com \
--to=mario.limonciello@amd.com \
--cc=Shyam-sundar.S-k@amd.com \
--cc=bp@alien8.de \
--cc=gautham.shenoy@amd.com \
--cc=hdegoede@redhat.com \
--cc=ilpo.jarvinen@linux.intel.com \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=perry.yuan@amd.com \
--cc=platform-driver-x86@vger.kernel.org \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®