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From: Mario Limonciello <mario.limonciello@amd.com>
To: "Borislav Petkov" <bp@alien8.de>,
	"Hans de Goede" <hdegoede@redhat.com>,
	"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: <x86@kernel.org>, "Gautham R . Shenoy" <gautham.shenoy@amd.com>,
	"Mario Limonciello" <mario.limonciello@amd.com>,
	Perry Yuan <perry.yuan@amd.com>, <linux-kernel@vger.kernel.org>,
	<linux-doc@vger.kernel.org>, <linux-pm@vger.kernel.org>,
	<platform-driver-x86@vger.kernel.org>,
	"Shyam Sundar S K" <Shyam-sundar.S-k@amd.com>
Subject: [PATCH v3 11/14] x86/process: Clear hardware feedback history for AMD processors
Date: Tue, 15 Oct 2024 16:36:42 -0500	[thread overview]
Message-ID: <20241015213645.1476-12-mario.limonciello@amd.com> (raw)
In-Reply-To: <20241015213645.1476-1-mario.limonciello@amd.com>

From: Perry Yuan <perry.yuan@amd.com>

Incorporate a mechanism within the context switching code to reset
the hardware history for AMD processors. Specifically, when a task
is switched in, the class ID was read and reset the hardware workload
classification history of CPU firmware and then it start to trigger
workload classification for the next running thread.

Signed-off-by: Perry Yuan <perry.yuan@amd.com>
Co-developed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
 arch/x86/include/asm/hreset.h |  6 ++++++
 arch/x86/kernel/cpu/common.c  | 15 +++++++++++++++
 arch/x86/kernel/process_32.c  |  3 +++
 arch/x86/kernel/process_64.c  |  3 +++
 4 files changed, 27 insertions(+)
 create mode 100644 arch/x86/include/asm/hreset.h

diff --git a/arch/x86/include/asm/hreset.h b/arch/x86/include/asm/hreset.h
new file mode 100644
index 000000000000..ae1f72602bbd
--- /dev/null
+++ b/arch/x86/include/asm/hreset.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_X86_HRESET_H
+
+void reset_hardware_history_hetero(void);
+
+#endif /* _ASM_X86_HRESET_H */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 07a34d723505..887821e97e54 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -57,6 +57,7 @@
 #include <asm/mce.h>
 #include <asm/msr.h>
 #include <asm/cacheinfo.h>
+#include <asm/hreset.h>
 #include <asm/memtype.h>
 #include <asm/microcode.h>
 #include <asm/intel-family.h>
@@ -403,6 +404,7 @@ static const unsigned long cr4_pinned_mask = X86_CR4_SMEP | X86_CR4_SMAP | X86_C
 					     X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED;
 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
 static unsigned long cr4_pinned_bits __ro_after_init;
+static DEFINE_STATIC_KEY_FALSE_RO(hardware_history_features);
 
 void native_write_cr0(unsigned long val)
 {
@@ -481,6 +483,12 @@ void cr4_init(void)
 	this_cpu_write(cpu_tlbstate.cr4, cr4);
 }
 
+static void __init setup_hreset(struct cpuinfo_x86 *c)
+{
+	if (cpu_feature_enabled(X86_FEATURE_WORKLOAD_CLASS))
+		static_key_enable_cpuslocked(&hardware_history_features.key);
+}
+
 /*
  * Once CPU feature detection is finished (and boot params have been
  * parsed), record any of the sensitive CR bits that are set, and
@@ -1844,6 +1852,7 @@ static void identify_cpu(struct cpuinfo_x86 *c)
 	setup_smep(c);
 	setup_smap(c);
 	setup_umip(c);
+	setup_hreset(c);
 
 	/* Enable FSGSBASE instructions if available. */
 	if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
@@ -2410,3 +2419,9 @@ void __init arch_cpu_finalize_init(void)
 	 */
 	mem_encrypt_init();
 }
+
+__always_inline void reset_hardware_history_hetero(void)
+{
+	if (static_branch_unlikely(&hardware_history_features))
+		wrmsrl(AMD_WORKLOAD_HRST, 0x1);
+}
diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index 0917c7f25720..6a3a1339f7a7 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -52,6 +52,7 @@
 #include <asm/switch_to.h>
 #include <asm/vm86.h>
 #include <asm/resctrl.h>
+#include <asm/hreset.h>
 #include <asm/proto.h>
 
 #include "process.h"
@@ -213,6 +214,8 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
 	/* Load the Intel cache allocation PQR MSR. */
 	resctrl_sched_in(next_p);
 
+	reset_hardware_history_hetero();
+
 	return prev_p;
 }
 
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 226472332a70..ea7f765c6262 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -54,6 +54,7 @@
 #include <asm/xen/hypervisor.h>
 #include <asm/vdso.h>
 #include <asm/resctrl.h>
+#include <asm/hreset.h>
 #include <asm/unistd.h>
 #include <asm/fsgsbase.h>
 #include <asm/fred.h>
@@ -709,6 +710,8 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
 	/* Load the Intel cache allocation PQR MSR. */
 	resctrl_sched_in(next_p);
 
+	reset_hardware_history_hetero();
+
 	return prev_p;
 }
 
-- 
2.43.0


  parent reply	other threads:[~2024-10-15 21:37 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-15 21:36 [PATCH v3 00/14] Add support for AMD hardware feedback interface Mario Limonciello
2024-10-15 21:36 ` [PATCH v3 01/14] Documentation: x86: Add AMD Hardware Feedback Interface documentation Mario Limonciello
2024-10-15 21:36 ` [PATCH v3 02/14] MAINTAINERS: Add maintainer entry for AMD Hardware Feedback Driver Mario Limonciello
2024-10-15 21:36 ` [PATCH v3 03/14] x86/cpufeatures: add X86_FEATURE_WORKLOAD_CLASS feature bit Mario Limonciello
2024-10-17  4:47   ` Gautham R. Shenoy
2024-10-22 12:42   ` Borislav Petkov
2024-10-22 13:03     ` Mario Limonciello
2024-10-15 21:36 ` [PATCH v3 04/14] x86/msr-index: define AMD heterogeneous CPU related MSR Mario Limonciello
2024-10-17  4:48   ` Gautham R. Shenoy
2024-10-15 21:36 ` [PATCH v3 05/14] platform/x86: hfi: Introduce AMD Hardware Feedback Interface Driver Mario Limonciello
2024-10-17  6:07   ` Gautham R. Shenoy
2024-10-15 21:36 ` [PATCH v3 06/14] platform/x86: hfi: parse CPU core ranking data from shared memory Mario Limonciello
2024-10-15 21:36 ` [PATCH v3 07/14] platform/x86: hfi: init per-cpu scores for each class Mario Limonciello
2024-10-17  5:52   ` Gautham R. Shenoy
2024-10-15 21:36 ` [PATCH v3 08/14] platform/x86: hfi: add online and offline callback support Mario Limonciello
2024-10-16 12:42   ` Ilpo Järvinen
2024-10-15 21:36 ` [PATCH v3 09/14] platform/x86: hfi: add power management callback Mario Limonciello
2024-10-17  6:00   ` Gautham R. Shenoy
2024-10-17 19:27     ` Mario Limonciello
2024-10-15 21:36 ` [PATCH v3 10/14] x86/cpu: Enable SD_ASYM_PACKING for DIE Domain on AMD Processors Mario Limonciello
2024-10-17  6:06   ` Gautham R. Shenoy
2024-10-15 21:36 ` Mario Limonciello [this message]
2024-10-15 21:36 ` [PATCH v3 12/14] cpufreq/amd-pstate: Disable preferred cores on designs with workload classification Mario Limonciello
2024-10-15 21:36 ` [PATCH v3 13/14] platform/x86/amd: hfi: Set ITMT priority from ranking data Mario Limonciello
2024-10-15 21:36 ` [PATCH v3 14/14] platform/x86: hfi: Add debugfs support Mario Limonciello
2024-10-16 12:38   ` Ilpo Järvinen
2024-10-16 16:09     ` Mario Limonciello

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