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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Rob Clark <robdclark@gmail.com>,
	 Abhinav Kumar <quic_abhinavk@quicinc.com>,
	Sean Paul <sean@poorly.run>,
	 Marijn Suijten <marijn.suijten@somainline.org>,
	 David Airlie <airlied@gmail.com>,
	Simona Vetter <simona@ffwll.ch>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
	 freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 4/8] drm/msm/dpu: use single CTL if it is the only CTL returned by RM
Date: Fri, 28 Feb 2025 06:14:08 +0200	[thread overview]
Message-ID: <20250228-dpu-active-ctl-v2-4-9a9df2ee5193@linaro.org> (raw)
In-Reply-To: <20250228-dpu-active-ctl-v2-0-9a9df2ee5193@linaro.org>

On DPU >= 5.0 CTL blocks were reworked in order to support using a
single CTL for all outputs. In preparation of reworking the RM code to
return single CTL make sure that dpu_encoder can cope with that.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 32992e9525530ea4dec2f46643fc06d40d3bca7b..e7dad94d91a7b6e99adb9aadb48aa8cd164babfa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1288,7 +1288,11 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
 			return;
 		}
 
-		phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL;
+		/* Use first (and only) CTL if active CTLs are supported */
+		if (num_ctl == 1)
+			phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[0]);
+		else
+			phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL;
 		if (!phys->hw_ctl) {
 			DPU_ERROR_ENC(dpu_enc,
 				"no ctl block assigned at idx: %d\n", i);

-- 
2.39.5


  parent reply	other threads:[~2025-02-28  4:14 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-28  4:14 [PATCH v2 0/8] drm/msm/dpu: improve CTL handling on DPU >= 5.0 platforms Dmitry Baryshkov
2025-02-28  4:14 ` [PATCH v2 1/8] drm/msm/dpu: don't overwrite CTL_MERGE_3D_ACTIVE register Dmitry Baryshkov
2025-02-28  4:14 ` [PATCH v2 2/8] drm/msm/dpu: program master INTF value Dmitry Baryshkov
2025-02-28  9:23   ` Marijn Suijten
2025-02-28 10:16     ` Dmitry Baryshkov
2025-02-28  4:14 ` [PATCH v2 3/8] drm/msm/dpu: pass master interface to CTL configuration Dmitry Baryshkov
2025-02-28  4:14 ` Dmitry Baryshkov [this message]
2025-02-28  4:14 ` [PATCH v2 5/8] drm/msm/dpu: don't select single flush for active CTL blocks Dmitry Baryshkov
2025-02-28  4:14 ` [PATCH v2 6/8] drm/msm/dpu: allocate single CTL for DPU >= 5.0 Dmitry Baryshkov
2025-02-28  4:14 ` [PATCH v2 7/8] drm/msm/dpu: remove DPU_CTL_SPLIT_DISPLAY from CTL blocks on " Dmitry Baryshkov
2025-02-28  4:14 ` [PATCH v2 8/8] drm/msm/dpu: drop now-unused condition for has_legacy_ctls Dmitry Baryshkov
2025-02-28  9:08   ` Marijn Suijten
2025-02-28  8:34 ` [PATCH v2 0/8] drm/msm/dpu: improve CTL handling on DPU >= 5.0 platforms neil.armstrong

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