From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Rob Clark <robdclark@gmail.com>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>,
Simona Vetter <simona@ffwll.ch>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 8/8] drm/msm/dpu: drop now-unused condition for has_legacy_ctls
Date: Fri, 28 Feb 2025 06:14:12 +0200 [thread overview]
Message-ID: <20250228-dpu-active-ctl-v2-8-9a9df2ee5193@linaro.org> (raw)
In-Reply-To: <20250228-dpu-active-ctl-v2-0-9a9df2ee5193@linaro.org>
Now as we have dropped the DPU_CTL_SPLIT_DISPLAY from DPU >= 5.0
configuration, drop the rm->has_legacy_ctl condition which short-cutted
the check for those platforms.
Suggested-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Note, it is imposible to reoder commits in any other sensible way. The
DPU_CTL_SPLIT_DISPLAY can not be dropped before the patch that enables
single-CTL support.
---
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 4dbc9bc7eb4f151f83055220665ee5fd238ae7ba..2557effe639b5360bc948a49b0cccdb59ee35dab 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -410,8 +410,7 @@ static int _dpu_rm_reserve_ctls(
DPU_DEBUG("ctl %d caps 0x%lX\n", j + CTL_0, features);
- if (rm->has_legacy_ctls &&
- needs_split_display != has_split_display)
+ if (needs_split_display != has_split_display)
continue;
ctl_idx[i] = j;
--
2.39.5
next prev parent reply other threads:[~2025-02-28 4:14 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-28 4:14 [PATCH v2 0/8] drm/msm/dpu: improve CTL handling on DPU >= 5.0 platforms Dmitry Baryshkov
2025-02-28 4:14 ` [PATCH v2 1/8] drm/msm/dpu: don't overwrite CTL_MERGE_3D_ACTIVE register Dmitry Baryshkov
2025-02-28 4:14 ` [PATCH v2 2/8] drm/msm/dpu: program master INTF value Dmitry Baryshkov
2025-02-28 9:23 ` Marijn Suijten
2025-02-28 10:16 ` Dmitry Baryshkov
2025-02-28 4:14 ` [PATCH v2 3/8] drm/msm/dpu: pass master interface to CTL configuration Dmitry Baryshkov
2025-02-28 4:14 ` [PATCH v2 4/8] drm/msm/dpu: use single CTL if it is the only CTL returned by RM Dmitry Baryshkov
2025-02-28 4:14 ` [PATCH v2 5/8] drm/msm/dpu: don't select single flush for active CTL blocks Dmitry Baryshkov
2025-02-28 4:14 ` [PATCH v2 6/8] drm/msm/dpu: allocate single CTL for DPU >= 5.0 Dmitry Baryshkov
2025-02-28 4:14 ` [PATCH v2 7/8] drm/msm/dpu: remove DPU_CTL_SPLIT_DISPLAY from CTL blocks on " Dmitry Baryshkov
2025-02-28 4:14 ` Dmitry Baryshkov [this message]
2025-02-28 9:08 ` [PATCH v2 8/8] drm/msm/dpu: drop now-unused condition for has_legacy_ctls Marijn Suijten
2025-02-28 8:34 ` [PATCH v2 0/8] drm/msm/dpu: improve CTL handling on DPU >= 5.0 platforms neil.armstrong
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