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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Rob Clark <robdclark@gmail.com>,
	 Abhinav Kumar <quic_abhinavk@quicinc.com>,
	Sean Paul <sean@poorly.run>,
	 Marijn Suijten <marijn.suijten@somainline.org>,
	 David Airlie <airlied@gmail.com>,
	Simona Vetter <simona@ffwll.ch>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
	 freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 5/8] drm/msm/dpu: don't select single flush for active CTL blocks
Date: Fri, 28 Feb 2025 06:14:09 +0200	[thread overview]
Message-ID: <20250228-dpu-active-ctl-v2-5-9a9df2ee5193@linaro.org> (raw)
In-Reply-To: <20250228-dpu-active-ctl-v2-0-9a9df2ee5193@linaro.org>

In case of ACTIVE CTLs, a single CTL is being used for flushing all INTF
blocks. Don't skip programming the CTL on those targets.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 232055473ba55998b79dd2e8c752c129bbffbff4..8a618841e3ea89acfe4a42d48319a6c54a1b3495 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -374,7 +374,8 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg)
 static bool dpu_encoder_phys_vid_needs_single_flush(
 		struct dpu_encoder_phys *phys_enc)
 {
-	return phys_enc->split_role != ENC_ROLE_SOLO;
+	return !(phys_enc->hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) &&
+		phys_enc->split_role != ENC_ROLE_SOLO;
 }
 
 static void dpu_encoder_phys_vid_atomic_mode_set(

-- 
2.39.5


  parent reply	other threads:[~2025-02-28  4:14 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-28  4:14 [PATCH v2 0/8] drm/msm/dpu: improve CTL handling on DPU >= 5.0 platforms Dmitry Baryshkov
2025-02-28  4:14 ` [PATCH v2 1/8] drm/msm/dpu: don't overwrite CTL_MERGE_3D_ACTIVE register Dmitry Baryshkov
2025-02-28  4:14 ` [PATCH v2 2/8] drm/msm/dpu: program master INTF value Dmitry Baryshkov
2025-02-28  9:23   ` Marijn Suijten
2025-02-28 10:16     ` Dmitry Baryshkov
2025-02-28  4:14 ` [PATCH v2 3/8] drm/msm/dpu: pass master interface to CTL configuration Dmitry Baryshkov
2025-02-28  4:14 ` [PATCH v2 4/8] drm/msm/dpu: use single CTL if it is the only CTL returned by RM Dmitry Baryshkov
2025-02-28  4:14 ` Dmitry Baryshkov [this message]
2025-02-28  4:14 ` [PATCH v2 6/8] drm/msm/dpu: allocate single CTL for DPU >= 5.0 Dmitry Baryshkov
2025-02-28  4:14 ` [PATCH v2 7/8] drm/msm/dpu: remove DPU_CTL_SPLIT_DISPLAY from CTL blocks on " Dmitry Baryshkov
2025-02-28  4:14 ` [PATCH v2 8/8] drm/msm/dpu: drop now-unused condition for has_legacy_ctls Dmitry Baryshkov
2025-02-28  9:08   ` Marijn Suijten
2025-02-28  8:34 ` [PATCH v2 0/8] drm/msm/dpu: improve CTL handling on DPU >= 5.0 platforms neil.armstrong

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