* [PATCH v2 2/5] arm64: dts: ti: k3-am62a-phycore-som: Add boot phase tags
2025-03-05 8:55 [PATCH v2 1/5] arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags Wadim Egorov
@ 2025-03-05 8:55 ` Wadim Egorov
2025-03-05 8:55 ` [PATCH v2 3/5] arm64: dts: ti: k3-am642-phyboard-electra: " Wadim Egorov
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Wadim Egorov @ 2025-03-05 8:55 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, upstream
The bootph-all and bootph-pre-ram tags were introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across different
boot phases.
Add boot phase tags to all required nodes to ensure boot support from
all sources, including UART, USB (DFU), Ethernet, uSD card, eMMC, and
OSPI NOR Flash.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
v1: http://lists.infradead.org/pipermail/linux-arm-kernel/2025-February/1006241.html
v2:
- Add bootph-all to cpsw_port1 & main_pktdma
- Drop bootph-all from cpsw3g
---
arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
index a5aceaa39670..7920559e84a3 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
@@ -42,6 +42,7 @@ memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+ bootph-all;
};
reserved-memory {
@@ -99,6 +100,7 @@ main_i2c0_pins_default: main-i2c0-default-pins {
AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (D17) I2C0_SCL */
AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (E16) I2C0_SDA */
>;
+ bootph-all;
};
main_mdio1_pins_default: main-mdio1-default-pins {
@@ -106,6 +108,7 @@ main_mdio1_pins_default: main-mdio1-default-pins {
AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
>;
+ bootph-all;
};
main_mmc0_pins_default: main-mmc0-default-pins {
@@ -121,6 +124,7 @@ AM62AX_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (W7) MMC0_DAT5 */
AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (W9) MMC0_DAT6 */
AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AB8) MMC0_DAT7 */
>;
+ bootph-all;
};
main_rgmii1_pins_default: main-rgmii1-default-pins {
@@ -138,6 +142,7 @@ AM62AX_IOPAD(0x140, PIN_OUTPUT, 0) /* (AA17) RGMII1_TD3 */
AM62AX_IOPAD(0x130, PIN_OUTPUT, 0) /* (AB17) RGMII1_TXC */
AM62AX_IOPAD(0x12c, PIN_OUTPUT, 0) /* (W16) RGMII1_TX_CTL */
>;
+ bootph-all;
};
ospi0_pins_default: ospi0-default-pins {
@@ -155,6 +160,7 @@ AM62AX_IOPAD(0x024, PIN_INPUT, 0) /* (J20) OSPI0_D6 */
AM62AX_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (L21) OSPI0_DQS */
>;
+ bootph-all;
};
pmic_irq_pins_default: pmic-irq-default-pins {
@@ -168,11 +174,13 @@ &cpsw3g {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_rgmii1_pins_default>;
+ status = "okay";
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
+ bootph-all;
};
&cpsw3g_mdio {
@@ -182,6 +190,7 @@ &cpsw3g_mdio {
cpsw3g_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
reg = <1>;
+ bootph-all;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
@@ -196,6 +205,7 @@ &main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
+ bootph-all;
status = "okay";
pmic@30 {
@@ -302,6 +312,10 @@ &main_gpio_intr {
status = "okay";
};
+&main_pktdma {
+ bootph-all;
+};
+
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
@@ -318,6 +332,7 @@ serial_flash: flash@0 {
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
+ bootph-all;
};
};
@@ -326,5 +341,6 @@ &sdhci0 {
pinctrl-0 = <&main_mmc0_pins_default>;
disable-wp;
non-removable;
+ bootph-all;
status = "okay";
};
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v2 3/5] arm64: dts: ti: k3-am642-phyboard-electra: Add boot phase tags
2025-03-05 8:55 [PATCH v2 1/5] arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags Wadim Egorov
2025-03-05 8:55 ` [PATCH v2 2/5] arm64: dts: ti: k3-am62a-phycore-som: " Wadim Egorov
@ 2025-03-05 8:55 ` Wadim Egorov
2025-03-05 8:55 ` [PATCH v2 4/5] arm64: dts: ti: k3-am642-phyboard-electra: Reorder properties per DTS coding style Wadim Egorov
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Wadim Egorov @ 2025-03-05 8:55 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, upstream
The bootph-all and bootph-pre-ram tags were introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across different
boot phases.
Add boot phase tags to all required nodes to ensure boot support from
all sources, including UART, Ethernet, uSD card, eMMC, and OSPI NOR Flash.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
v1: http://lists.infradead.org/pipermail/linux-arm-kernel/2025-February/1006243.html
v2:
- Add bootph-all to main_pktdma
- Drop bootph-all from cpsw3g
---
arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 15 +++++++++++++++
.../boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 5 +++++
2 files changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
index 99a6fdfaa7fb..74423ca3204f 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
@@ -27,6 +27,7 @@ aliases {
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+ bootph-all;
};
reserved_memory: reserved-memory {
@@ -132,6 +133,7 @@ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x0100, PIN_OUTPUT, 7) /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */
>;
+ bootph-all;
};
cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins {
@@ -150,6 +152,7 @@ AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) PRG1_PRU1_GPO19.GPIO0_84 */
>;
+ bootph-all;
};
eeprom_wp_pins_default: eeprom-wp-default-pins {
@@ -169,6 +172,7 @@ main_i2c0_pins_default: main-i2c0-default-pins {
AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */
>;
+ bootph-all;
};
ospi0_pins_default: ospi0-default-pins {
@@ -185,6 +189,7 @@ AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
>;
+ bootph-all;
};
rtc_pins_default: rtc-defaults-pins {
@@ -204,6 +209,7 @@ &cpsw3g_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cpsw_mdio_pins_default>;
+ bootph-all;
cpsw3g_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
@@ -215,12 +221,14 @@ cpsw3g_phy1: ethernet-phy@1 {
reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
+ bootph-all;
};
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
+ bootph-all;
status = "okay";
};
@@ -266,6 +274,7 @@ &main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
+ bootph-all;
eeprom@50 {
compatible = "atmel,24c32";
@@ -330,6 +339,10 @@ vdda_1v8: ldo1 {
};
};
+&main_pktdma {
+ bootph-all;
+};
+
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
@@ -377,6 +390,7 @@ serial_flash: flash@0 {
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
+ bootph-all;
};
};
@@ -386,6 +400,7 @@ &sdhci0 {
ti,driver-strength-ohm = <50>;
disable-wp;
keep-power-in-suspend;
+ bootph-all;
};
&tscadc0 {
diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
index bc8e1ce11047..6fbd8d932396 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
@@ -171,6 +171,7 @@ vcc_3v3_mmc: regulator-sd {
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
+ bootph-all;
};
};
@@ -275,6 +276,7 @@ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
>;
+ bootph-all;
};
main_spi0_pins_default: main-spi0-default-pins {
@@ -291,6 +293,7 @@ main_uart0_pins_default: main-uart0-default-pins {
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
>;
+ bootph-all;
};
main_uart1_pins_default: main-uart1-default-pins {
@@ -413,6 +416,7 @@ &main_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
+ bootph-all;
};
&main_uart1 {
@@ -429,6 +433,7 @@ &sdhci1 {
pinctrl-0 = <&main_mmc1_pins_default>;
disable-wp;
no-1-8-v;
+ bootph-all;
};
&serdes0 {
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v2 4/5] arm64: dts: ti: k3-am642-phyboard-electra: Reorder properties per DTS coding style
2025-03-05 8:55 [PATCH v2 1/5] arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags Wadim Egorov
2025-03-05 8:55 ` [PATCH v2 2/5] arm64: dts: ti: k3-am62a-phycore-som: " Wadim Egorov
2025-03-05 8:55 ` [PATCH v2 3/5] arm64: dts: ti: k3-am642-phyboard-electra: " Wadim Egorov
@ 2025-03-05 8:55 ` Wadim Egorov
2025-03-05 8:55 ` [PATCH v2 5/5] arm64: dts: ti: k3-am62a-phycore-som: " Wadim Egorov
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Wadim Egorov @ 2025-03-05 8:55 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, upstream
Reorder properties to comply with the DeviceTree coding style guidelines:
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
v2: No changes
---
arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 12 ++++++------
.../boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 14 +++++++-------
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
index 74423ca3204f..5d7da292eeb9 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
@@ -206,22 +206,22 @@ &cpsw3g {
};
&cpsw3g_mdio {
- status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cpsw_mdio_pins_default>;
bootph-all;
+ status = "okay";
cpsw3g_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&main_gpio0>;
interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
bootph-all;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
@@ -270,11 +270,11 @@ mbox_m4_0: mbox-m4-0 {
};
&main_i2c0 {
- status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
bootph-all;
+ status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
@@ -375,9 +375,9 @@ &mcu_m4fss {
};
&ospi0 {
- status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
+ status = "okay";
serial_flash: flash@0 {
compatible = "jedec,spi-nor";
@@ -395,12 +395,12 @@ serial_flash: flash@0 {
};
&sdhci0 {
- status = "okay";
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
keep-power-in-suspend;
bootph-all;
+ status = "okay";
};
&tscadc0 {
diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
index 6fbd8d932396..f63c101b7d61 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
@@ -352,10 +352,10 @@ &i2c_som_rtc {
};
&main_i2c1 {
- status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
+ status = "okay";
eeprom@51 {
compatible = "atmel,24c02";
@@ -385,25 +385,25 @@ led-5 {
};
&main_mcan0 {
- status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mcan0_pins_default>;
phys = <&can_tc1>;
+ status = "okay";
};
&main_mcan1 {
- status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mcan1_pins_default>;
phys = <&can_tc2>;
+ status = "okay";
};
&main_spi0 {
- status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_spi0_pins_default>;
cs-gpios = <0>, <&main_gpio1 43 GPIO_ACTIVE_LOW>;
ti,pindir-d0-out-d1-in;
+ status = "okay";
tpm@1 {
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
@@ -413,27 +413,27 @@ tpm@1 {
};
&main_uart0 {
- status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
bootph-all;
+ status = "okay";
};
&main_uart1 {
- status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
uart-has-rtscts;
+ status = "okay";
};
&sdhci1 {
- status = "okay";
vmmc-supply = <&vcc_3v3_mmc>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
disable-wp;
no-1-8-v;
bootph-all;
+ status = "okay";
};
&serdes0 {
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v2 5/5] arm64: dts: ti: k3-am62a-phycore-som: Reorder properties per DTS coding style
2025-03-05 8:55 [PATCH v2 1/5] arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags Wadim Egorov
` (2 preceding siblings ...)
2025-03-05 8:55 ` [PATCH v2 4/5] arm64: dts: ti: k3-am642-phyboard-electra: Reorder properties per DTS coding style Wadim Egorov
@ 2025-03-05 8:55 ` Wadim Egorov
2025-03-07 10:36 ` [PATCH v2 1/5] arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags Vignesh Raghavendra
2025-03-28 15:21 ` Nishanth Menon
5 siblings, 0 replies; 7+ messages in thread
From: Wadim Egorov @ 2025-03-05 8:55 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: linux-arm-kernel, devicetree, linux-kernel, upstream
Reorder properties to comply with the DeviceTree coding style guidelines:
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
v2: No changes
---
arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
index 7920559e84a3..147d56b87984 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
@@ -171,7 +171,6 @@ AM62AX_IOPAD(0x1f4, PIN_INPUT, 0) /* (D16) EXTINTn */
};
&cpsw3g {
- status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_rgmii1_pins_default>;
status = "okay";
@@ -225,8 +224,8 @@ pmic@30 {
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
- ti,power-button;
system-power-controller;
+ ti,power-button;
regulators {
vdd_3v3: buck1 {
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v2 1/5] arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags
2025-03-05 8:55 [PATCH v2 1/5] arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags Wadim Egorov
` (3 preceding siblings ...)
2025-03-05 8:55 ` [PATCH v2 5/5] arm64: dts: ti: k3-am62a-phycore-som: " Wadim Egorov
@ 2025-03-07 10:36 ` Vignesh Raghavendra
2025-03-28 15:21 ` Nishanth Menon
5 siblings, 0 replies; 7+ messages in thread
From: Vignesh Raghavendra @ 2025-03-07 10:36 UTC (permalink / raw)
To: nm, kristo, robh, krzk+dt, conor+dt, Wadim Egorov
Cc: Vignesh Raghavendra, linux-arm-kernel, devicetree, linux-kernel,
upstream
Hi Wadim Egorov,
On Wed, 05 Mar 2025 09:55:33 +0100, Wadim Egorov wrote:
> The bootph-all and bootph-pre-ram tags were introduced in dt-schema
> (dtschema/schemas/bootph.yaml) to define node usage across different
> boot phases.
>
> Add boot phase tags to all required nodes to ensure boot support from
> all sources, including UART, USB (DFU), Ethernet, uSD card, eMMC, and
> OSPI NOR Flash.
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/5] arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags
commit: c2d18ec0ea4ce9d6d8be5a1a9b266f57a40b5e24
[2/5] arm64: dts: ti: k3-am62a-phycore-som: Add boot phase tags
commit: a5965ee0107a37ca4c73f05f06f55dad759572d2
[3/5] arm64: dts: ti: k3-am642-phyboard-electra: Add boot phase tags
commit: a9c8485cd13cdffee5bdcda6b625f678900994c4
[4/5] arm64: dts: ti: k3-am642-phyboard-electra: Reorder properties per DTS coding style
commit: 61a12b5a9923e4beec5595fed3b9c3d5c0c25c32
[5/5] arm64: dts: ti: k3-am62a-phycore-som: Reorder properties per DTS coding style
commit: a89d3f47b09c793d0454350739ee8695ff30fb5c
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v2 1/5] arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags
2025-03-05 8:55 [PATCH v2 1/5] arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags Wadim Egorov
` (4 preceding siblings ...)
2025-03-07 10:36 ` [PATCH v2 1/5] arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags Vignesh Raghavendra
@ 2025-03-28 15:21 ` Nishanth Menon
5 siblings, 0 replies; 7+ messages in thread
From: Nishanth Menon @ 2025-03-28 15:21 UTC (permalink / raw)
To: Wadim Egorov
Cc: vigneshr, kristo, robh, krzk+dt, conor+dt, linux-arm-kernel,
devicetree, linux-kernel, upstream
On 09:55-20250305, Wadim Egorov wrote:
> The bootph-all and bootph-pre-ram tags were introduced in dt-schema
> (dtschema/schemas/bootph.yaml) to define node usage across different
> boot phases.
>
> Add boot phase tags to all required nodes to ensure boot support from
> all sources, including UART, USB (DFU), Ethernet, uSD card, eMMC, and
> OSPI NOR Flash.
>
> Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
> ---
> v1: http://lists.infradead.org/pipermail/linux-arm-kernel/2025-February/1006239.html
> v2:
> - Add bootph-all to cpsw_port1 and main_pktma
> - Remove bootph-all from cpsw3g
> ---
> arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 15 +++++++++++++++
> .../arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi | 9 +++++++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
> index 2ef4cbaec789..effab2f810c2 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
> @@ -29,6 +29,7 @@ aliases {
> memory@80000000 {
> device_type = "memory";
> reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
> + bootph-all;
> };
>
> reserved_memory: reserved-memory {
> @@ -131,6 +132,7 @@ main_i2c0_pins_default: main-i2c0-default-pins {
> AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
> AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
> >;
> + bootph-all;
> };
>
> main_mdio1_pins_default: main-mdio1-default-pins {
> @@ -138,6 +140,7 @@ main_mdio1_pins_default: main-mdio1-default-pins {
> AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
> AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
> >;
> + bootph-all;
> };
>
> main_mmc0_pins_default: main-mmc0-default-pins {
> @@ -153,6 +156,7 @@ AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
> AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
> AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
> >;
> + bootph-all;
> };
>
> main_rgmii1_pins_default: main-rgmii1-default-pins {
> @@ -170,6 +174,7 @@ AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
> AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
> AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
> >;
> + bootph-all;
> };
>
> ospi0_pins_default: ospi0-default-pins {
> @@ -186,6 +191,7 @@ AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
> AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
> AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
> >;
> + bootph-all;
> };
>
> pmic_irq_pins_default: pmic-irq-default-pins {
> @@ -210,6 +216,7 @@ &cpsw3g {
> &cpsw_port1 {
> phy-mode = "rgmii-rxid";
> phy-handle = <&cpsw3g_phy1>;
> + bootph-all;
> };
>
> &cpsw3g_mdio {
> @@ -220,6 +227,7 @@ &cpsw3g_mdio {
> cpsw3g_phy1: ethernet-phy@1 {
> compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
> reg = <1>;
> + bootph-all;
> ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> };
> @@ -232,10 +240,15 @@ mbox_m4_0: mbox-m4-0 {
> };
> };
>
> +&main_pktdma {
> + bootph-all;
> +};
> +
> &main_i2c0 {
> pinctrl-names = "default";
> pinctrl-0 = <&main_i2c0_pins_default>;
> clock-frequency = <400000>;
> + bootph-all;
please review closer the series to ensure that no parent node has a
bootph property if the child node has it.
> status = "okay";
>
> pmic@30 {
> @@ -355,6 +368,7 @@ serial_flash: flash@0 {
> cdns,tchsh-ns = <60>;
> cdns,tslch-ns = <60>;
> cdns,read-delay = <0>;
> + bootph-all;
> };
> };
>
> @@ -363,5 +377,6 @@ &sdhci0 {
> pinctrl-0 = <&main_mmc0_pins_default>;
> disable-wp;
> non-removable;
> + bootph-all;
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi
> index 922cad14c9f8..aab74d6019b0 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi
> @@ -138,6 +138,7 @@ vcc_3v3_mmc: regulator-vcc-3v3-mmc {
> regulator-max-microvolt = <3300000>;
> regulator-always-on;
> regulator-boot-on;
> + bootph-all;
> };
>
> vcc_3v3_sw: regulator-vcc-3v3-sw {
> @@ -233,6 +234,7 @@ AM62X_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (C21) MMC1_DAT2 */
> AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */
> AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */
> >;
> + bootph-all;
> };
>
> main_rgmii2_pins_default: main-rgmii2-default-pins {
> @@ -257,6 +259,7 @@ main_uart0_pins_default: main-uart0-default-pins {
> AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
> AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
> >;
> + bootph-all;
> };
>
> main_uart1_pins_default: main-uart1-default-pins {
> @@ -266,6 +269,7 @@ AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
> AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
> AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
> >;
> + bootph-pre-ram;
> };
>
> main_usb1_pins_default: main-usb1-default-pins {
> @@ -430,12 +434,14 @@ &main_mcan0 {
> &main_uart0 {
> pinctrl-names = "default";
> pinctrl-0 = <&main_uart0_pins_default>;
> + bootph-all;
> status = "okay";
> };
>
> &main_uart1 {
> pinctrl-names = "default";
> pinctrl-0 = <&main_uart1_pins_default>;
> + bootph-pre-ram;
> /* Main UART1 may be used by TIFS firmware */
> status = "okay";
> };
> @@ -467,11 +473,13 @@ &sdhci1 {
> pinctrl-0 = <&main_mmc1_pins_default>;
> disable-wp;
> no-1-8-v;
> + bootph-all;
> status = "okay";
> };
>
> &usbss0 {
> ti,vbus-divider;
> + bootph-all;
> status = "okay";
> };
>
> @@ -482,6 +490,7 @@ &usbss1 {
>
> &usb0 {
> usb-role-switch;
> + bootph-all;
>
> port {
> typec_hs: endpoint {
> --
> 2.34.1
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 7+ messages in thread