* [PATCH v4 0/2] x86: Prepare for new Intel Family numbers @ 2025-03-18 22:38 Sohil Mehta 2025-03-18 22:38 ` [PATCH v4 1/2] perf/x86: Simplify Intel PMU initialization Sohil Mehta 2025-03-18 22:38 ` [PATCH v4 2/2] perf/x86/p4: Replace Pentium 4 model checks with VFM ones Sohil Mehta 0 siblings, 2 replies; 5+ messages in thread From: Sohil Mehta @ 2025-03-18 22:38 UTC (permalink / raw) To: x86, Ingo Molnar, Kan Liang Cc: Dave Hansen, Tony Luck, Peter Zijlstra, Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland, Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter, Thomas Gleixner, Borislav Petkov, H . Peter Anvin, Rafael J . Wysocki, Len Brown, Andy Lutomirski, Viresh Kumar, Jean Delvare, Guenter Roeck, Zhang Rui, Andrew Cooper, Dapeng Mi, Sohil Mehta, linux-perf-users, linux-kernel ---Summary--- Mainstream Intel processors have been using Family 6 for a couple of decades. This series is an audit of all the arch/x86 Intel Family-model checks to get ready for the upcoming Family 18 and 19 models. It also converts one of the last remaining Intel-specific x86_model checks to VFM ones. Most of the patches were picked up from the v3 series and applied to tip. This series contains the remaining perf/x86 patches rebased on tip:x86/cpu. ---v4 changes--- * Addressed comments from Kan Liang. * Picked up Kan Liang's review tags. * Rebased on top of tip:x86/cpu. ---Previous versions--- Refer to the v2 cover letter for more background. v3: https://lore.kernel.org/lkml/20250219184133.816753-1-sohil.mehta@intel.com/ v2: https://lore.kernel.org/lkml/20250211194407.2577252-1-sohil.mehta@intel.com/ RFC-v1: https://lore.kernel.org/lkml/20241220213711.1892696-1-sohil.mehta@intel.com/ Sohil Mehta (2): perf/x86: Simplify Intel PMU initialization perf/x86/p4: Replace Pentium 4 model checks with VFM ones arch/x86/events/intel/core.c | 14 ++++++++++---- arch/x86/events/intel/p4.c | 7 ++++--- arch/x86/events/intel/p6.c | 26 +++----------------------- arch/x86/include/asm/intel-family.h | 1 + 4 files changed, 18 insertions(+), 30 deletions(-) base-commit: 08d9bb5b0d89826fedc5204c8bd2463220465996 -- 2.43.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v4 1/2] perf/x86: Simplify Intel PMU initialization 2025-03-18 22:38 [PATCH v4 0/2] x86: Prepare for new Intel Family numbers Sohil Mehta @ 2025-03-18 22:38 ` Sohil Mehta 2025-03-19 21:00 ` [tip: x86/core] perf/x86/intel, x86/cpu: " tip-bot2 for Sohil Mehta 2025-03-18 22:38 ` [PATCH v4 2/2] perf/x86/p4: Replace Pentium 4 model checks with VFM ones Sohil Mehta 1 sibling, 1 reply; 5+ messages in thread From: Sohil Mehta @ 2025-03-18 22:38 UTC (permalink / raw) To: x86, Ingo Molnar, Kan Liang Cc: Dave Hansen, Tony Luck, Peter Zijlstra, Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland, Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter, Thomas Gleixner, Borislav Petkov, H . Peter Anvin, Rafael J . Wysocki, Len Brown, Andy Lutomirski, Viresh Kumar, Jean Delvare, Guenter Roeck, Zhang Rui, Andrew Cooper, Dapeng Mi, Sohil Mehta, linux-perf-users, linux-kernel Architectural Perfmon was introduced on the Family 6 "Core" processors starting with Yonah. Processors before Yonah need their own customized PMU initialization. p6_pmu_init() is expected to provide that initialization for early Family 6 processors. But, currently, it could get called for any Family 6 processor if the architectural perfmon feature is disabled on that processor. To simplify, restrict the P6 PMU initialization to early Family 6 processors that do not have architectural perfmon support and truly need the special handling. As a result, the "unsupported" console print becomes practically unreachable because all the released P6 processors are covered by the switch cases. Move the console print to a common location where it can cover all modern processors (including Family >15) that may not have architectural perfmon support enumerated. Also, use this opportunity to get rid of the unnecessary switch cases in P6 initialization. Only the Pentium Pro processor needs a quirk, and the rest of the processors do not need any special handling. The gaps in the case numbers are only due to no processor with those model numbers being released. Use decimal numbers to represent Intel Family numbers. Also, convert one of the last few Intel x86_model comparisons to a VFM-based one. Signed-off-by: Sohil Mehta <sohil.mehta@intel.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> --- v4: Move the default case outside of the switch. Pickup the Reviewed-by tag from Kan Liang. v3: Restrict calling p6_pmu_init() to only when needed. Move the console print to a common location. v2: No change. --- arch/x86/events/intel/core.c | 14 ++++++++++---- arch/x86/events/intel/p6.c | 26 +++----------------------- 2 files changed, 13 insertions(+), 27 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 40a62bf6ef0a..49a1155e6cb9 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -6541,15 +6541,21 @@ __init int intel_pmu_init(void) char *name; struct x86_hybrid_pmu *pmu; + /* Architectural Perfmon was introduced starting with Core "Yonah" */ if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { switch (boot_cpu_data.x86) { - case 0x6: - return p6_pmu_init(); - case 0xb: + case 6: + if (boot_cpu_data.x86_vfm < INTEL_CORE_YONAH) + return p6_pmu_init(); + break; + case 11: return knc_pmu_init(); - case 0xf: + case 15: return p4_pmu_init(); } + + pr_cont("unsupported CPU family %d model %d ", + boot_cpu_data.x86, boot_cpu_data.x86_model); return -ENODEV; } diff --git a/arch/x86/events/intel/p6.c b/arch/x86/events/intel/p6.c index a6cffb4f4ef5..65b45e9d7016 100644 --- a/arch/x86/events/intel/p6.c +++ b/arch/x86/events/intel/p6.c @@ -2,6 +2,8 @@ #include <linux/perf_event.h> #include <linux/types.h> +#include <asm/cpu_device_id.h> + #include "../perf_event.h" /* @@ -248,30 +250,8 @@ __init int p6_pmu_init(void) { x86_pmu = p6_pmu; - switch (boot_cpu_data.x86_model) { - case 1: /* Pentium Pro */ + if (boot_cpu_data.x86_vfm == INTEL_PENTIUM_PRO) x86_add_quirk(p6_pmu_rdpmc_quirk); - break; - - case 3: /* Pentium II - Klamath */ - case 5: /* Pentium II - Deschutes */ - case 6: /* Pentium II - Mendocino */ - break; - - case 7: /* Pentium III - Katmai */ - case 8: /* Pentium III - Coppermine */ - case 10: /* Pentium III Xeon */ - case 11: /* Pentium III - Tualatin */ - break; - - case 9: /* Pentium M - Banias */ - case 13: /* Pentium M - Dothan */ - break; - - default: - pr_cont("unsupported p6 CPU model %d ", boot_cpu_data.x86_model); - return -ENODEV; - } memcpy(hw_cache_event_ids, p6_hw_cache_event_ids, sizeof(hw_cache_event_ids)); -- 2.43.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [tip: x86/core] perf/x86/intel, x86/cpu: Simplify Intel PMU initialization 2025-03-18 22:38 ` [PATCH v4 1/2] perf/x86: Simplify Intel PMU initialization Sohil Mehta @ 2025-03-19 21:00 ` tip-bot2 for Sohil Mehta 0 siblings, 0 replies; 5+ messages in thread From: tip-bot2 for Sohil Mehta @ 2025-03-19 21:00 UTC (permalink / raw) To: linux-tip-commits Cc: Sohil Mehta, Ingo Molnar, Kan Liang, Peter Zijlstra, x86, linux-kernel The following commit has been merged into the x86/core branch of tip: Commit-ID: 8b70c7436f51ac0f4702b466e1d9db938944e641 Gitweb: https://git.kernel.org/tip/8b70c7436f51ac0f4702b466e1d9db938944e641 Author: Sohil Mehta <sohil.mehta@intel.com> AuthorDate: Tue, 18 Mar 2025 22:38:27 Committer: Ingo Molnar <mingo@kernel.org> CommitterDate: Wed, 19 Mar 2025 21:34:09 +01:00 perf/x86/intel, x86/cpu: Simplify Intel PMU initialization Architectural Perfmon was introduced on the Family 6 "Core" processors starting with Yonah. Processors before Yonah need their own customized PMU initialization. p6_pmu_init() is expected to provide that initialization for early Family 6 processors. But, currently, it could get called for any Family 6 processor if the architectural perfmon feature is disabled on that processor. To simplify, restrict the P6 PMU initialization to early Family 6 processors that do not have architectural perfmon support and truly need the special handling. As a result, the "unsupported" console print becomes practically unreachable because all the released P6 processors are covered by the switch cases. Move the console print to a common location where it can cover all modern processors (including Family >15) that may not have architectural perfmon support enumerated. Also, use this opportunity to get rid of the unnecessary switch cases in P6 initialization. Only the Pentium Pro processor needs a quirk, and the rest of the processors do not need any special handling. The gaps in the case numbers are only due to no processor with those model numbers being released. Use decimal numbers to represent Intel Family numbers. Also, convert one of the last few Intel x86_model comparisons to a VFM-based one. Signed-off-by: Sohil Mehta <sohil.mehta@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/20250318223828.2945651-2-sohil.mehta@intel.com --- arch/x86/events/intel/core.c | 14 ++++++++++---- arch/x86/events/intel/p6.c | 26 +++----------------------- 2 files changed, 13 insertions(+), 27 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 40a62bf..49a1155 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -6541,15 +6541,21 @@ __init int intel_pmu_init(void) char *name; struct x86_hybrid_pmu *pmu; + /* Architectural Perfmon was introduced starting with Core "Yonah" */ if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { switch (boot_cpu_data.x86) { - case 0x6: - return p6_pmu_init(); - case 0xb: + case 6: + if (boot_cpu_data.x86_vfm < INTEL_CORE_YONAH) + return p6_pmu_init(); + break; + case 11: return knc_pmu_init(); - case 0xf: + case 15: return p4_pmu_init(); } + + pr_cont("unsupported CPU family %d model %d ", + boot_cpu_data.x86, boot_cpu_data.x86_model); return -ENODEV; } diff --git a/arch/x86/events/intel/p6.c b/arch/x86/events/intel/p6.c index a6cffb4..65b45e9 100644 --- a/arch/x86/events/intel/p6.c +++ b/arch/x86/events/intel/p6.c @@ -2,6 +2,8 @@ #include <linux/perf_event.h> #include <linux/types.h> +#include <asm/cpu_device_id.h> + #include "../perf_event.h" /* @@ -248,30 +250,8 @@ __init int p6_pmu_init(void) { x86_pmu = p6_pmu; - switch (boot_cpu_data.x86_model) { - case 1: /* Pentium Pro */ + if (boot_cpu_data.x86_vfm == INTEL_PENTIUM_PRO) x86_add_quirk(p6_pmu_rdpmc_quirk); - break; - - case 3: /* Pentium II - Klamath */ - case 5: /* Pentium II - Deschutes */ - case 6: /* Pentium II - Mendocino */ - break; - - case 7: /* Pentium III - Katmai */ - case 8: /* Pentium III - Coppermine */ - case 10: /* Pentium III Xeon */ - case 11: /* Pentium III - Tualatin */ - break; - - case 9: /* Pentium M - Banias */ - case 13: /* Pentium M - Dothan */ - break; - - default: - pr_cont("unsupported p6 CPU model %d ", boot_cpu_data.x86_model); - return -ENODEV; - } memcpy(hw_cache_event_ids, p6_hw_cache_event_ids, sizeof(hw_cache_event_ids)); ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v4 2/2] perf/x86/p4: Replace Pentium 4 model checks with VFM ones 2025-03-18 22:38 [PATCH v4 0/2] x86: Prepare for new Intel Family numbers Sohil Mehta 2025-03-18 22:38 ` [PATCH v4 1/2] perf/x86: Simplify Intel PMU initialization Sohil Mehta @ 2025-03-18 22:38 ` Sohil Mehta 2025-03-19 21:00 ` [tip: x86/core] perf/x86/intel, x86/cpu: " tip-bot2 for Sohil Mehta 1 sibling, 1 reply; 5+ messages in thread From: Sohil Mehta @ 2025-03-18 22:38 UTC (permalink / raw) To: x86, Ingo Molnar, Kan Liang Cc: Dave Hansen, Tony Luck, Peter Zijlstra, Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland, Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter, Thomas Gleixner, Borislav Petkov, H . Peter Anvin, Rafael J . Wysocki, Len Brown, Andy Lutomirski, Viresh Kumar, Jean Delvare, Guenter Roeck, Zhang Rui, Andrew Cooper, Dapeng Mi, Sohil Mehta, linux-perf-users, linux-kernel Introduce a name for an old Pentium 4 model and replace the x86_model checks with VFM ones. This gets rid of one of the last remaining Intel-specific x86_model checks. Signed-off-by: Sohil Mehta <sohil.mehta@intel.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> --- v4: Pickup the Reviewed-by tag from Kan Liang. v3: No change. v2: No change. --- arch/x86/events/intel/p4.c | 7 ++++--- arch/x86/include/asm/intel-family.h | 1 + 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/p4.c b/arch/x86/events/intel/p4.c index 844bc4fc4724..fb726c6fc6e7 100644 --- a/arch/x86/events/intel/p4.c +++ b/arch/x86/events/intel/p4.c @@ -10,6 +10,7 @@ #include <linux/perf_event.h> #include <asm/perf_event_p4.h> +#include <asm/cpu_device_id.h> #include <asm/hardirq.h> #include <asm/apic.h> @@ -732,9 +733,9 @@ static bool p4_event_match_cpu_model(unsigned int event_idx) { /* INSTR_COMPLETED event only exist for model 3, 4, 6 (Prescott) */ if (event_idx == P4_EVENT_INSTR_COMPLETED) { - if (boot_cpu_data.x86_model != 3 && - boot_cpu_data.x86_model != 4 && - boot_cpu_data.x86_model != 6) + if (boot_cpu_data.x86_vfm != INTEL_P4_PRESCOTT && + boot_cpu_data.x86_vfm != INTEL_P4_PRESCOTT_2M && + boot_cpu_data.x86_vfm != INTEL_P4_CEDARMILL) return false; } diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 6cd08da64684..3a97a7eefb51 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -193,6 +193,7 @@ /* Family 15 - NetBurst */ #define INTEL_P4_WILLAMETTE IFM(15, 0x01) /* Also Xeon Foster */ #define INTEL_P4_PRESCOTT IFM(15, 0x03) +#define INTEL_P4_PRESCOTT_2M IFM(15, 0x04) #define INTEL_P4_CEDARMILL IFM(15, 0x06) /* Also Xeon Dempsey */ /* Family 19 */ -- 2.43.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [tip: x86/core] perf/x86/intel, x86/cpu: Replace Pentium 4 model checks with VFM ones 2025-03-18 22:38 ` [PATCH v4 2/2] perf/x86/p4: Replace Pentium 4 model checks with VFM ones Sohil Mehta @ 2025-03-19 21:00 ` tip-bot2 for Sohil Mehta 0 siblings, 0 replies; 5+ messages in thread From: tip-bot2 for Sohil Mehta @ 2025-03-19 21:00 UTC (permalink / raw) To: linux-tip-commits Cc: Sohil Mehta, Ingo Molnar, Kan Liang, Peter Zijlstra, x86, linux-kernel The following commit has been merged into the x86/core branch of tip: Commit-ID: de844ef582e3a5e0cbd429c68b6079eeb87394e5 Gitweb: https://git.kernel.org/tip/de844ef582e3a5e0cbd429c68b6079eeb87394e5 Author: Sohil Mehta <sohil.mehta@intel.com> AuthorDate: Tue, 18 Mar 2025 22:38:28 Committer: Ingo Molnar <mingo@kernel.org> CommitterDate: Wed, 19 Mar 2025 21:34:10 +01:00 perf/x86/intel, x86/cpu: Replace Pentium 4 model checks with VFM ones Introduce a name for an old Pentium 4 model and replace the x86_model checks with VFM ones. This gets rid of one of the last remaining Intel-specific x86_model checks. Signed-off-by: Sohil Mehta <sohil.mehta@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/20250318223828.2945651-3-sohil.mehta@intel.com --- arch/x86/events/intel/p4.c | 7 ++++--- arch/x86/include/asm/intel-family.h | 1 + 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/p4.c b/arch/x86/events/intel/p4.c index 844bc4f..fb726c6 100644 --- a/arch/x86/events/intel/p4.c +++ b/arch/x86/events/intel/p4.c @@ -10,6 +10,7 @@ #include <linux/perf_event.h> #include <asm/perf_event_p4.h> +#include <asm/cpu_device_id.h> #include <asm/hardirq.h> #include <asm/apic.h> @@ -732,9 +733,9 @@ static bool p4_event_match_cpu_model(unsigned int event_idx) { /* INSTR_COMPLETED event only exist for model 3, 4, 6 (Prescott) */ if (event_idx == P4_EVENT_INSTR_COMPLETED) { - if (boot_cpu_data.x86_model != 3 && - boot_cpu_data.x86_model != 4 && - boot_cpu_data.x86_model != 6) + if (boot_cpu_data.x86_vfm != INTEL_P4_PRESCOTT && + boot_cpu_data.x86_vfm != INTEL_P4_PRESCOTT_2M && + boot_cpu_data.x86_vfm != INTEL_P4_CEDARMILL) return false; } diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 6cd08da..3a97a7e 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -193,6 +193,7 @@ /* Family 15 - NetBurst */ #define INTEL_P4_WILLAMETTE IFM(15, 0x01) /* Also Xeon Foster */ #define INTEL_P4_PRESCOTT IFM(15, 0x03) +#define INTEL_P4_PRESCOTT_2M IFM(15, 0x04) #define INTEL_P4_CEDARMILL IFM(15, 0x06) /* Also Xeon Dempsey */ /* Family 19 */ ^ permalink raw reply [flat|nested] 5+ messages in thread
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