From: "Chang S. Bae" <chang.seok.bae@intel.com>
To: linux-kernel@vger.kernel.org
Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com,
bp@alien8.de, dave.hansen@linux.intel.com,
chang.seok.bae@intel.com
Subject: [PATCH RFC v2 2/9] x86/fpu/xstate: Introduce xfeature order table and accessor macro
Date: Thu, 20 Mar 2025 16:42:53 -0700 [thread overview]
Message-ID: <20250320234301.8342-3-chang.seok.bae@intel.com> (raw)
In-Reply-To: <20250320234301.8342-1-chang.seok.bae@intel.com>
The kernel has largely assumed that higher xstate component numbers
correspond to later offsets in the buffer. However, this assumption no
longer holds for the non-compacted format, where a newer state component
may have a lower offset.
When iterating over xstate components in offset order, using the feature
number as an index may be misleading. At the same time, the CPU exposes
each component’s size and offset based on its feature number, making it a
key for state information.
To provide flexibility in handling xstate ordering, introduce a mapping
table: feature order -> feature number. The table is dynamically
populated based on the CPU-exposed features and is sorted in offset order
at boot time.
Additionally, add an accessor macro to facilitate sequential traversal of
xstate components based on their actual buffer positions, given a feature
bitmask. This accessor macro will be particularly useful for computing
custom non-compacted format sizes and iterating over xstate offsets in
non-compacted buffers.
Suggested-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Link: https://lore.kernel.org/all/7fa02be2-0884-4702-ae73-a3620938161b@intel.com
---
RFC-V1 -> RFC-V2: Populate the order table dynamically (Dave).
This introduction lays the groundwork for handling APX, which is assigned
feature number 19 but appears immediately after FEATURE_YMM in
APX-enabled systems. Older CPUs, such as Skylake systems, previously used
this region for MPX.
Later in this series, APX and MPX will be explicitly marked as mutually
exclusive to prevent conflicts. Since the xfeature order table is
dynamically populated at boot, it will reflect the correct feature set
for each system configuration.
---
arch/x86/kernel/fpu/xstate.c | 58 +++++++++++++++++++++++++++++++-----
1 file changed, 50 insertions(+), 8 deletions(-)
diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
index 542c6981180d..1e22103a8e17 100644
--- a/arch/x86/kernel/fpu/xstate.c
+++ b/arch/x86/kernel/fpu/xstate.c
@@ -14,6 +14,7 @@
#include <linux/proc_fs.h>
#include <linux/vmalloc.h>
#include <linux/coredump.h>
+#include <linux/sort.h>
#include <asm/fpu/api.h>
#include <asm/fpu/regset.h>
@@ -88,6 +89,31 @@ static unsigned int xstate_sizes[XFEATURE_MAX] __ro_after_init =
{ [ 0 ... XFEATURE_MAX - 1] = -1};
static unsigned int xstate_flags[XFEATURE_MAX] __ro_after_init;
+/*
+ * Ordering of xstate components in uncompacted format: The xfeature
+ * number does not necessarily indicate its position in the XSAVE buffer.
+ * This array defines the traversal order of xstate features.
+ */
+static unsigned int xfeature_uncompact_order[XFEATURE_MAX] __ro_after_init =
+ { [ 0 ... XFEATURE_MAX - 1] = -1};
+
+static inline unsigned int next_xfeature_order(unsigned int i, u64 mask)
+{
+ for (; xfeature_uncompact_order[i] != -1; i++) {
+ if (mask & BIT_ULL(xfeature_uncompact_order[i]))
+ break;
+ }
+
+ return i;
+}
+
+/* Iterate xstate features in uncompacted order: */
+#define for_each_extended_xfeature_in_order(i, mask) \
+ for (i = 0; \
+ i = next_xfeature_order(i, mask), \
+ xfeature_uncompact_order[i] != -1; \
+ i++)
+
#define XSTATE_FLAG_SUPERVISOR BIT(0)
#define XSTATE_FLAG_ALIGNED64 BIT(1)
@@ -209,13 +235,20 @@ static bool xfeature_enabled(enum xfeature xfeature)
return fpu_kernel_cfg.max_features & BIT_ULL(xfeature);
}
+static int compare_xstate_offsets(const void *xfeature1, const void *xfeature2)
+{
+ return xstate_offsets[*(unsigned int *)xfeature1] -
+ xstate_offsets[*(unsigned int *)xfeature2];
+}
+
/*
* Record the offsets and sizes of various xstates contained
- * in the XSAVE state memory layout.
+ * in the XSAVE state memory layout. Also, create an ordered
+ * list of xfeatures for handling out-of-order offsets.
*/
static void __init setup_xstate_cache(void)
{
- u32 eax, ebx, ecx, edx, i;
+ u32 eax, ebx, ecx, edx, xfeature, i = 0;
/*
* The FP xstates and SSE xstates are legacy states. They are always
* in the fixed offsets in the xsave area in either compacted form
@@ -229,21 +262,30 @@ static void __init setup_xstate_cache(void)
xstate_sizes[XFEATURE_SSE] = sizeof_field(struct fxregs_state,
xmm_space);
- for_each_extended_xfeature(i, fpu_kernel_cfg.max_features) {
- cpuid_count(CPUID_LEAF_XSTATE, i, &eax, &ebx, &ecx, &edx);
+ for_each_extended_xfeature(xfeature, fpu_kernel_cfg.max_features) {
+ cpuid_count(CPUID_LEAF_XSTATE, xfeature, &eax, &ebx, &ecx, &edx);
- xstate_sizes[i] = eax;
- xstate_flags[i] = ecx;
+ xstate_sizes[xfeature] = eax;
+ xstate_flags[xfeature] = ecx;
/*
* If an xfeature is supervisor state, the offset in EBX is
* invalid, leave it to -1.
*/
- if (xfeature_is_supervisor(i))
+ if (xfeature_is_supervisor(xfeature))
continue;
- xstate_offsets[i] = ebx;
+ xstate_offsets[xfeature] = ebx;
+
+ /* Populate the list of xfeatures before sorting */
+ xfeature_uncompact_order[i++] = xfeature;
}
+
+ /*
+ * Sort xfeatures by their offsets to support out-of-order
+ * offsets in the uncompacted format.
+ */
+ sort(xfeature_uncompact_order, i, sizeof(unsigned int), compare_xstate_offsets, NULL);
}
/*
--
2.45.2
next prev parent reply other threads:[~2025-03-20 23:43 UTC|newest]
Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-27 18:44 [PATCH RFC v1 00/11] x86: Support Intel Advanced Performance Extensions Chang S. Bae
2025-02-27 18:44 ` [PATCH RFC v1 01/11] x86/fpu/xstate: Simplify print_xstate_features() Chang S. Bae
2025-02-27 18:51 ` Dave Hansen
2025-02-27 18:52 ` Ingo Molnar
2025-02-27 19:04 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
2025-02-27 18:44 ` [PATCH RFC v1 02/11] x86/fpu/xstate: Introduce xstate order table and accessor macro Chang S. Bae
2025-02-27 19:03 ` Dave Hansen
2025-02-27 19:34 ` Andrew Cooper
2025-02-27 19:42 ` Ingo Molnar
2025-03-20 23:46 ` Chang S. Bae
2025-02-27 19:05 ` Ingo Molnar
2025-02-27 19:32 ` Dave Hansen
2025-02-27 19:36 ` Ingo Molnar
2025-02-27 19:49 ` Andrew Cooper
2025-02-27 20:06 ` Ingo Molnar
2025-02-27 21:10 ` Andrew Cooper
2025-02-27 21:28 ` Ingo Molnar
2025-02-27 21:30 ` Ingo Molnar
2025-02-27 22:23 ` Andrew Cooper
2025-02-28 3:10 ` Chang S. Bae
2025-02-28 17:11 ` Ingo Molnar
2025-02-27 19:56 ` Dave Hansen
2025-02-27 20:02 ` Ingo Molnar
2025-02-27 20:19 ` Dave Hansen
2025-02-27 20:29 ` Ingo Molnar
2025-02-27 21:17 ` Dave Hansen
2025-02-27 21:37 ` Ingo Molnar
2025-02-27 23:54 ` Dave Hansen
2025-02-28 15:20 ` Sean Christopherson
2025-02-27 18:44 ` [PATCH RFC v1 03/11] x86/fpu/xstate: Remove xstate offset check Chang S. Bae
2025-02-27 18:44 ` [PATCH RFC v1 04/11] x86/fpu/xstate: Adjust XSAVE buffer size calculation Chang S. Bae
2025-02-27 18:44 ` [PATCH RFC v1 05/11] x86/fpu/xstate: Adjust xstate copying logic for user ABI Chang S. Bae
2025-02-27 18:44 ` [PATCH RFC v1 06/11] x86/fpu/mpx: Remove MPX xstate component support Chang S. Bae
2025-02-27 19:12 ` Ingo Molnar
2025-02-28 3:12 ` Chang S. Bae
2025-03-20 23:47 ` Chang S. Bae
2025-04-01 17:13 ` Chang S. Bae
2025-02-27 18:44 ` [PATCH RFC v1 07/11] x86/cpufeatures: Add X86_FEATURE_APX Chang S. Bae
2025-02-27 18:44 ` [PATCH RFC v1 08/11] x86/fpu/apx: Define APX state component Chang S. Bae
2025-02-27 18:44 ` [PATCH RFC v1 09/11] x86/fpu/apx: Disallow conflicting MPX presence Chang S. Bae
2025-02-27 23:16 ` Dave Hansen
2025-02-27 23:58 ` Chang S. Bae
2025-02-27 18:44 ` [PATCH RFC v1 10/11] x86/fpu/apx: Enable APX state support Chang S. Bae
2025-02-27 18:44 ` [PATCH RFC v1 11/11] selftests/x86/apx: Add APX test Chang S. Bae
2025-02-27 19:15 ` [PATCH RFC v1 00/11] x86: Support Intel Advanced Performance Extensions Ingo Molnar
2025-02-27 19:36 ` Dave Hansen
2025-02-28 3:10 ` Chang S. Bae
2025-03-20 23:42 ` [PATCH RFC v2 0/9] " Chang S. Bae
2025-03-20 23:42 ` [PATCH RFC v2 1/9] x86/fpu/xstate: Remove xstate offset check Chang S. Bae
2025-03-25 10:18 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
2025-04-14 7:34 ` [tip: x86/merge] " tip-bot2 for Chang S. Bae
2025-03-20 23:42 ` Chang S. Bae [this message]
2025-03-25 10:18 ` [tip: x86/fpu] x86/fpu/xstate: Introduce xfeature order table and accessor macro tip-bot2 for Chang S. Bae
2025-04-14 7:34 ` [tip: x86/merge] " tip-bot2 for Chang S. Bae
2025-03-20 23:42 ` [PATCH RFC v2 3/9] x86/fpu/xstate: Adjust XSAVE buffer size calculation Chang S. Bae
2025-03-25 10:28 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
2025-04-14 7:34 ` [tip: x86/merge] " tip-bot2 for Chang S. Bae
2025-03-20 23:42 ` [PATCH RFC v2 4/9] x86/fpu/xstate: Adjust xstate copying logic for user ABI Chang S. Bae
2025-03-25 10:18 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
2025-03-25 10:28 ` tip-bot2 for Chang S. Bae
2025-04-14 7:34 ` [tip: x86/merge] " tip-bot2 for Chang S. Bae
2025-03-20 23:42 ` [PATCH RFC v2 5/9] x86/cpufeatures: Add X86_FEATURE_APX Chang S. Bae
2025-04-11 16:12 ` [PATCH RFC v2a " Chang S. Bae
2025-04-11 16:54 ` Sohil Mehta
2025-04-11 18:23 ` Chang S. Bae
2025-04-11 21:57 ` Sohil Mehta
2025-04-12 8:43 ` Ingo Molnar
2025-04-14 8:23 ` Ingo Molnar
2025-04-14 17:28 ` Sohil Mehta
2025-04-14 17:32 ` Dave Hansen
2025-04-14 17:45 ` Sohil Mehta
2025-04-14 18:02 ` Chang S. Bae
2025-04-14 18:12 ` Sohil Mehta
2025-04-14 18:31 ` Chang S. Bae
2025-04-16 2:16 ` [PATCH 00/10] x86/fpu: APX enablement and assorted FPU code improvements Chang S. Bae
2025-04-16 2:16 ` [PATCH 01/10] x86/cpufeatures: Add X86_FEATURE_APX Chang S. Bae
2025-04-16 8:17 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
2025-04-16 2:16 ` [PATCH 02/10] x86/fpu/apx: Define APX state component Chang S. Bae
2025-04-16 8:17 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
2025-04-16 2:16 ` [PATCH 03/10] x86/fpu/apx: Disallow conflicting MPX presence Chang S. Bae
2025-04-16 8:17 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
2025-04-16 2:16 ` [PATCH 04/10] x86/fpu/apx: Enable APX state support Chang S. Bae
2025-04-16 8:17 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
2025-04-16 2:16 ` [PATCH 05/10] selftests/x86/apx: Add APX test Chang S. Bae
2025-04-16 8:17 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
2025-04-16 2:16 ` [PATCH 06/10] x86/fpu: Log XSAVE disablement consistently Chang S. Bae
2025-04-16 8:17 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
2025-04-16 16:56 ` [PATCH 06/10] " Sohil Mehta
2025-04-16 17:03 ` Chang S. Bae
2025-04-16 18:04 ` Sohil Mehta
2025-04-16 2:16 ` [PATCH 07/10] x86/fpu: Refactor xfeature bitmask update code for sigframe XSAVE Chang S. Bae
2025-04-16 8:05 ` Ingo Molnar
2025-04-16 16:55 ` Chang S. Bae
2025-04-16 8:17 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
2025-04-16 2:16 ` [PATCH 08/10] x86/pkeys: Simplify PKRU update in signal frame Chang S. Bae
2025-04-16 8:17 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
2025-04-16 2:16 ` [PATCH 09/10] x86/fpu: Remove export of mxcsr_feature_mask Chang S. Bae
2025-04-16 8:17 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
2025-04-16 2:17 ` [PATCH 10/10] x86/fpu: Rename fpu_reset_fpregs() to fpu_reset_fpstate_regs() Chang S. Bae
2025-04-16 8:17 ` [tip: x86/fpu] " tip-bot2 for Chang S. Bae
2025-04-16 8:07 ` [PATCH 00/10] x86/fpu: APX enablement and assorted FPU code improvements Ingo Molnar
2025-04-16 16:56 ` Chang S. Bae
2025-03-20 23:42 ` [PATCH RFC v2 6/9] x86/fpu/apx: Define APX state component Chang S. Bae
2025-04-11 22:54 ` Sohil Mehta
2025-03-20 23:42 ` [PATCH RFC v2 7/9] x86/fpu/apx: Disallow conflicting MPX presence Chang S. Bae
2025-04-14 17:09 ` Sohil Mehta
2025-04-14 17:25 ` Dave Hansen
2025-03-20 23:42 ` [PATCH RFC v2 8/9] x86/fpu/apx: Enable APX state support Chang S. Bae
2025-04-14 15:41 ` Sohil Mehta
2025-03-20 23:43 ` [PATCH RFC v2 9/9] selftests/x86/apx: Add APX test Chang S. Bae
2025-04-14 16:02 ` Sohil Mehta
2025-03-25 10:25 ` [PATCH RFC v2 0/9] x86: Support Intel Advanced Performance Extensions Ingo Molnar
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