From: James Morse <james.morse@arm.com>
To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
"Rafael J . Wysocki" <rafael@kernel.org>,
sudeep.holla@arm.com, Rob Herring <robh@kernel.org>,
Ben Horgan <ben.horgan@arm.com>,
James Morse <james.morse@arm.com>
Subject: [PATCH 1/5] cacheinfo: Set cache 'id' based on DT data
Date: Fri, 13 Jun 2025 13:03:52 +0000 [thread overview]
Message-ID: <20250613130356.8080-2-james.morse@arm.com> (raw)
In-Reply-To: <20250613130356.8080-1-james.morse@arm.com>
From: Rob Herring <robh@kernel.org>
Use the minimum CPU h/w id of the CPUs associated with the cache for the
cache 'id'. This will provide a stable id value for a given system. As
we need to check all possible CPUs, we can't use the shared_cpu_map
which is just online CPUs. As there's not a cache to CPUs mapping in DT,
we have to walk all CPU nodes and then walk cache levels.
The cache_id exposed to user-space has historically been 32 bits, and
is too late to change. Give up on assigning cache-id's if a CPU h/w
id greater than 32 bits is found.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
[ ben: converted to use the __free cleanup idiom ]
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
[ morse: Add checks to give up if a value larger than 32 bits is seen. ]
Signed-off-by: James Morse <james.morse@arm.com>
---
Use as a 32bit value has been seen in DPDK patches here:
http://inbox.dpdk.org/dev/20241021015246.304431-2-wathsala.vithanage@arm.com/
---
drivers/base/cacheinfo.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index cf0d455209d7..9888d87840a2 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -8,6 +8,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/acpi.h>
+#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/cacheinfo.h>
#include <linux/compiler.h>
@@ -183,6 +184,37 @@ static bool cache_node_is_unified(struct cacheinfo *this_leaf,
return of_property_read_bool(np, "cache-unified");
}
+static void cache_of_set_id(struct cacheinfo *this_leaf, struct device_node *np)
+{
+ struct device_node *cpu;
+ u32 min_id = ~0;
+
+ for_each_of_cpu_node(cpu) {
+ struct device_node *cache_node __free(device_node) = of_find_next_cache_node(cpu);
+ u64 id = of_get_cpu_hwid(cpu, 0);
+
+ if (FIELD_GET(GENMASK_ULL(63, 32), id)) {
+ of_node_put(cpu);
+ return;
+ }
+ while (1) {
+ if (!cache_node)
+ break;
+ if (cache_node == np && id < min_id) {
+ min_id = id;
+ break;
+ }
+ struct device_node *prev __free(device_node) = cache_node;
+ cache_node = of_find_next_cache_node(cache_node);
+ }
+ }
+
+ if (min_id != ~0) {
+ this_leaf->id = min_id;
+ this_leaf->attributes |= CACHE_ID;
+ }
+}
+
static void cache_of_set_props(struct cacheinfo *this_leaf,
struct device_node *np)
{
@@ -198,6 +230,7 @@ static void cache_of_set_props(struct cacheinfo *this_leaf,
cache_get_line_size(this_leaf, np);
cache_nr_sets(this_leaf, np);
cache_associativity(this_leaf);
+ cache_of_set_id(this_leaf, np);
}
static int cache_setup_of_node(unsigned int cpu)
--
2.39.5
next prev parent reply other threads:[~2025-06-13 13:04 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-13 13:03 [PATCH 0/5] " James Morse
2025-06-13 13:03 ` James Morse [this message]
2025-06-17 16:03 ` [PATCH 1/5] " Jonathan Cameron
2025-06-23 14:18 ` Rob Herring
2025-06-27 16:38 ` James Morse
2025-06-13 13:03 ` [PATCH 2/5] cacheinfo: Add arch hook to compress CPU h/w id into 32 bits for cache-id James Morse
2025-06-17 16:05 ` Jonathan Cameron
2025-06-23 14:48 ` Rob Herring
2025-06-27 16:38 ` James Morse
2025-06-30 19:43 ` Rob Herring
2025-07-04 17:39 ` James Morse
2025-07-07 17:41 ` Rob Herring
2025-06-13 13:03 ` [PATCH 3/5] arm64: cacheinfo: Provide helper to compress MPIDR value into u32 James Morse
2025-06-17 16:14 ` Jonathan Cameron
2025-06-27 16:39 ` James Morse
2025-06-13 13:03 ` [PATCH 4/5] cacheinfo: Expose the code to generate a cache-id from a device_node James Morse
2025-06-17 16:21 ` Jonathan Cameron
2025-06-27 5:54 ` Shaopeng Tan (Fujitsu)
2025-06-27 16:39 ` James Morse
2025-06-27 16:38 ` James Morse
2025-06-13 13:03 ` [PATCH 5/5] cacheinfo: Add helper to find the cache size from cpu+level James Morse
2025-06-17 16:28 ` Jonathan Cameron
2025-06-27 16:38 ` James Morse
2025-06-23 15:05 ` [PATCH 0/5] cacheinfo: Set cache 'id' based on DT data Rob Herring
2025-06-27 16:38 ` James Morse
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