From: James Morse <james.morse@arm.com>
To: Rob Herring <robh@kernel.org>
Cc: linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
"Rafael J . Wysocki" <rafael@kernel.org>,
sudeep.holla@arm.com, Ben Horgan <ben.horgan@arm.com>
Subject: Re: [PATCH 0/5] cacheinfo: Set cache 'id' based on DT data
Date: Fri, 27 Jun 2025 17:38:48 +0100 [thread overview]
Message-ID: <efa92bef-8bfb-431f-ac9e-048041ff13f6@arm.com> (raw)
In-Reply-To: <CAL_JsqKD7yOxSnfnah2gE0EodtQ4KyJ2_qXmMu2oK9i6numzwA@mail.gmail.com>
Hi Rob,
On 23/06/2025 16:05, Rob Herring wrote:
> On Fri, Jun 13, 2025 at 8:04 AM James Morse <james.morse@arm.com> wrote:
>>
>> This series adds support for cache-ids to device-tree systems.
>> These values are exposed to user-space via
>> /sys/devices/system/cpu/cpuX/cache/indexY/id
>> and are used to identify caches and their associated CPUs by kernel interfaces
>> such as resctrl.
>>
>> Resctrl anticipates cache-ids are unique for a given cache level, but may
>> be sparse. See Documentation/filesystems/resctrl.rst's "Cache IDs" section.
>>
>> Another user is PCIe's cache-steering hints, where an id provided by the
>> hardware would be needed. Today this expects a platform specific ACPI hook
>> the program that value into the PCIe root port registers. If DT platforms
>> are ever supported, it will likely need a kernel driver to convert the
>> user-space cache-id to whatever hardware value is needed.
>>
>> Rob H previously preferred to generate a cache-id from the information DT
>> already has. (Rob: does the PCIe cache-steering use-case change this?)
> I don't think so because who knows what values the PCI root port
> needs.
Some hardware specific value, that would have to come from the DT...
> It's never going to be the cache id directly since that is per level.
Can re-used across levels, but because they can also be sparse its equally valid for them
to be unique. This is what is happening on arm64 ACPI platforms.
> So we'd need some sort of mapping. That's going to be something
> like this:
>
> Userspace level+id -> DT cache node -> PCI RP value
>
> So the first translation is the same as you have here. The 2nd
> translation might be something we put in DT or could be in PCI host
> bridge driver.
ACPI currently requires some kernel interaction too as the value gets written to some
platform specific register. Even if it did get standardised, I guess something like VFIO
would manage access to that register to fix up the values.
Thanks,
James
prev parent reply other threads:[~2025-06-27 16:38 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-13 13:03 James Morse
2025-06-13 13:03 ` [PATCH 1/5] " James Morse
2025-06-17 16:03 ` Jonathan Cameron
2025-06-23 14:18 ` Rob Herring
2025-06-27 16:38 ` James Morse
2025-06-13 13:03 ` [PATCH 2/5] cacheinfo: Add arch hook to compress CPU h/w id into 32 bits for cache-id James Morse
2025-06-17 16:05 ` Jonathan Cameron
2025-06-23 14:48 ` Rob Herring
2025-06-27 16:38 ` James Morse
2025-06-30 19:43 ` Rob Herring
2025-07-04 17:39 ` James Morse
2025-07-07 17:41 ` Rob Herring
2025-06-13 13:03 ` [PATCH 3/5] arm64: cacheinfo: Provide helper to compress MPIDR value into u32 James Morse
2025-06-17 16:14 ` Jonathan Cameron
2025-06-27 16:39 ` James Morse
2025-06-13 13:03 ` [PATCH 4/5] cacheinfo: Expose the code to generate a cache-id from a device_node James Morse
2025-06-17 16:21 ` Jonathan Cameron
2025-06-27 5:54 ` Shaopeng Tan (Fujitsu)
2025-06-27 16:39 ` James Morse
2025-06-27 16:38 ` James Morse
2025-06-13 13:03 ` [PATCH 5/5] cacheinfo: Add helper to find the cache size from cpu+level James Morse
2025-06-17 16:28 ` Jonathan Cameron
2025-06-27 16:38 ` James Morse
2025-06-23 15:05 ` [PATCH 0/5] cacheinfo: Set cache 'id' based on DT data Rob Herring
2025-06-27 16:38 ` James Morse [this message]
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