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From: James Morse <james.morse@arm.com>
To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	sudeep.holla@arm.com, Rob Herring <robh@kernel.org>,
	Ben Horgan <ben.horgan@arm.com>,
	James Morse <james.morse@arm.com>
Subject: [PATCH 5/5] cacheinfo: Add helper to find the cache size from cpu+level
Date: Fri, 13 Jun 2025 13:03:56 +0000	[thread overview]
Message-ID: <20250613130356.8080-6-james.morse@arm.com> (raw)
In-Reply-To: <20250613130356.8080-1-james.morse@arm.com>

The MPAM driver needs to know the size of a cache associated with a
particular CPU. The DT/ACPI agnostic way of doing this is to ask cacheinfo.

Add a helper to do this.

Signed-off-by: James Morse <james.morse@arm.com>
---
 include/linux/cacheinfo.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h
index 9c959caf8af8..3f1b6b2e25b5 100644
--- a/include/linux/cacheinfo.h
+++ b/include/linux/cacheinfo.h
@@ -148,6 +148,26 @@ static inline int get_cpu_cacheinfo_id(int cpu, int level)
 	return ci ? ci->id : -1;
 }
 
+/*
+ * Get the size of the cache associated with @cpu at level @level.
+ * cpuhp lock must be held.
+ */
+static inline unsigned int get_cpu_cacheinfo_size(int cpu, int level)
+{
+	struct cpu_cacheinfo *ci = get_cpu_cacheinfo(cpu);
+	int i;
+
+	if (!ci->info_list)
+		return 0;
+
+	for (i = 0; i < ci->num_leaves; i++) {
+		if (ci->info_list[i].level == level)
+			return ci->info_list[i].size;
+	}
+
+	return 0;
+}
+
 #if defined(CONFIG_ARM64) || defined(CONFIG_ARM)
 #define use_arch_cache_info()	(true)
 #else
-- 
2.39.5


  parent reply	other threads:[~2025-06-13 13:04 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-13 13:03 [PATCH 0/5] cacheinfo: Set cache 'id' based on DT data James Morse
2025-06-13 13:03 ` [PATCH 1/5] " James Morse
2025-06-17 16:03   ` Jonathan Cameron
2025-06-23 14:18     ` Rob Herring
2025-06-27 16:38       ` James Morse
2025-06-13 13:03 ` [PATCH 2/5] cacheinfo: Add arch hook to compress CPU h/w id into 32 bits for cache-id James Morse
2025-06-17 16:05   ` Jonathan Cameron
2025-06-23 14:48   ` Rob Herring
2025-06-27 16:38     ` James Morse
2025-06-30 19:43       ` Rob Herring
2025-07-04 17:39         ` James Morse
2025-07-07 17:41           ` Rob Herring
2025-06-13 13:03 ` [PATCH 3/5] arm64: cacheinfo: Provide helper to compress MPIDR value into u32 James Morse
2025-06-17 16:14   ` Jonathan Cameron
2025-06-27 16:39     ` James Morse
2025-06-13 13:03 ` [PATCH 4/5] cacheinfo: Expose the code to generate a cache-id from a device_node James Morse
2025-06-17 16:21   ` Jonathan Cameron
2025-06-27  5:54     ` Shaopeng Tan (Fujitsu)
2025-06-27 16:39       ` James Morse
2025-06-27 16:38     ` James Morse
2025-06-13 13:03 ` James Morse [this message]
2025-06-17 16:28   ` [PATCH 5/5] cacheinfo: Add helper to find the cache size from cpu+level Jonathan Cameron
2025-06-27 16:38     ` James Morse
2025-06-23 15:05 ` [PATCH 0/5] cacheinfo: Set cache 'id' based on DT data Rob Herring
2025-06-27 16:38   ` James Morse

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