[PATCH v6 0/3] Decouple max_pclk check from constant display feats

[PATCH v6 0/3] Decouple max_pclk check from constant display feats

[Swamil Jain]

In an effort to make the existing compatibles more usable, we are
removing the max_pclk_khz form dispc_features structure and doing the
supported pixel clock checks using clk_round_rate().

Changes are fully backwards compatible.

After integration of OLDI support[0], we need additional patches in
OLDI to identify the VP that has OLDI. We have to do this since
OLDI driver owns the VP clock (its serial clock) and we cannot perform
clock operations on those VP clock from tidss driver. This issue was
also reported upstream when DSI fixes[1] had some clock related calls
in tidss driver. When "clk_round_rate()" is called, ideally it should
have gone to "sci_clk_determine_rate()" to query DM but it doesn't since
clock is owned by OLDI not tidss.

So add a member is_ext_vp_clk[] in tidss_device structure to identify
this and avoid performing clock operations for VP if it has OLDI panel.
For the same checks in OLDI driver, atomic_check() hook is added to its
bridge_funcs.
In the atomic_check() chain, first the bridge_atomic_check() is called
and then crtc_atomic_check() is called. So mode clock is first checked
in oldi driver and then skipped in tidss driver.

Had the tidss_oldi structure been exposed to tidss_dispc.c, we could
have directly checked VP type in dispc but since the structure is defined
in tidss_oldi.c , we have to add additional member to tidss_device
structure.

[0]: https://lore.kernel.org/all/20250528122544.817829-1-aradhya.bhatia@linux.dev/
[1]: https://lore.kernel.org/all/DA6TT575Z82D.3MPK8HG5GRL8U@kernel.org/

Changelog v5->v6
- Drop caching logic
- Add comments for tolerance value
  (We are targeting another series for reducing tolerance value)
- Minor fixes in commit message

v5 patch link:
https://lore.kernel.org/all/20250819192113.2420396-1-s-jain1@ti.com/

Changelog v4->v5
- Rename is_oldi_vp[] to is_ext_vp_clk[]
- Store both pixel clock round_rate and attempted_rate to reduce
  clk_round_rate() calls while validating modes
- Code changes suggested by Tomi[2]
- Minor fixes in comments and commit message

[2]: https://lore.kernel.org/all/8cd9d1c4-2e9f-4766-b224-21925c4f991d@ideasonboard.com/

v4 patch link:
https://lore.kernel.org/all/20250704094851.182131-1-j-choudhary@ti.com/

Changelog v3->v4:
- Minor cosmetic fixes in code, comments and commit message
- Pick up R-by and add Fixes tag

v3 patch link:
https://lore.kernel.org/all/20250701095541.190422-1-j-choudhary@ti.com/

Changelog v2->v3:
- Add changes for OLDI
- Rename max_pclk as it is misleading
- Change commit message to make it more appropriate
- Drop unnecessary zero initialization

v2 patch link:
https://lore.kernel.org/all/20250618100509.20386-1-j-choudhary@ti.com/

Changelog v1->v2:
- Rebase it on linux-next after OLDI support series as all of its
  patches are reviewed and tested and it touches one of the functions
  used.
  
v1 patch link:
https://lore.kernel.org/all/20250618075804.139844-1-j-choudhary@ti.com/

Jayesh Choudhary (3):
  drm/tidss: oldi: Add property to identify OLDI supported VP
  drm/tidss: Remove max_pclk_khz from tidss display features:
  drm/tidss: oldi: Add atomic_check hook for oldi bridge

 drivers/gpu/drm/tidss/tidss_dispc.c | 78 +++++++++++------------------
 drivers/gpu/drm/tidss/tidss_dispc.h |  1 -
 drivers/gpu/drm/tidss/tidss_drv.h   |  1 +
 drivers/gpu/drm/tidss/tidss_oldi.c  | 23 +++++++++
 4 files changed, 54 insertions(+), 49 deletions(-)

[PATCH v6 1/3] drm/tidss: oldi: Add property to identify OLDI supported VP

[Swamil Jain]

From: Jayesh Choudhary <j-choudhary@ti.com>

TIDSS should know which VP has OLDI output to avoid calling clock
functions for that VP as those are controlled by oldi driver. Add a
property "is_ext_vp_clk" to "tidss_device" structure for that. Mark it
'true' in tidss_oldi_init() and 'false' in tidss_oldi_deinit().

Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support")
Tested-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Signed-off-by: Swamil Jain <s-jain1@ti.com>
---
 drivers/gpu/drm/tidss/tidss_drv.h  | 2 ++
 drivers/gpu/drm/tidss/tidss_oldi.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tidss_drv.h
index 84454a4855d1..e1c1f41d8b4b 100644
--- a/drivers/gpu/drm/tidss/tidss_drv.h
+++ b/drivers/gpu/drm/tidss/tidss_drv.h
@@ -24,6 +24,8 @@ struct tidss_device {
 
 	const struct dispc_features *feat;
 	struct dispc_device *dispc;
+	bool is_ext_vp_clk[TIDSS_MAX_PORTS];
+
 
 	unsigned int num_crtcs;
 	struct drm_crtc *crtcs[TIDSS_MAX_PORTS];
diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/tidss/tidss_oldi.c
index 7688251beba2..7ecbb2c3d0a2 100644
--- a/drivers/gpu/drm/tidss/tidss_oldi.c
+++ b/drivers/gpu/drm/tidss/tidss_oldi.c
@@ -430,6 +430,7 @@ void tidss_oldi_deinit(struct tidss_device *tidss)
 	for (int i = 0; i < tidss->num_oldis; i++) {
 		if (tidss->oldis[i]) {
 			drm_bridge_remove(&tidss->oldis[i]->bridge);
+			tidss->is_ext_vp_clk[tidss->oldis[i]->parent_vp] = false;
 			tidss->oldis[i] = NULL;
 		}
 	}
@@ -580,6 +581,7 @@ int tidss_oldi_init(struct tidss_device *tidss)
 		oldi->bridge.timings = &default_tidss_oldi_timings;
 
 		tidss->oldis[tidss->num_oldis++] = oldi;
+		tidss->is_ext_vp_clk[oldi->parent_vp] = true;
 		oldi->tidss = tidss;
 
 		drm_bridge_add(&oldi->bridge);

[PATCH v6 2/3] drm/tidss: Remove max_pclk_khz from tidss display features:

[Swamil Jain]

From: Jayesh Choudhary <j-choudhary@ti.com>

TIDSS hardware, by itself, does not have variable max pixel clock for
each VP. The maximum pixel clock is determined by the SoC's clocking
architecture.

The limitation that has been modeled until now comes from the SoC's
clocking architecture (PLL can only be programmed to a particular max
value). Instead of putting it as a constant field in dispc_features,
we can use clk_round_rate() to see if requested clock can be set or not.

Remove the constant "max_pclk_khz" from dispc_features. In mode_valid()
call, check if a best frequency match for the mode clock can be found
or not using clk_round_rate().

Since TIDSS display controller provides clock tolerance of 5%, we use
this while checking if the requested pixel clock is supported. Also,
move up dispc_pclk_diff() before it is called.

This will make the existing compatibles reusable if DSS features are
the same across two SoCs with the only difference being the pixel clock.

Note:
This uses clk_round_rate() to validate all modes and ensure that the
driver enumerates only those whose clocking requirements are well
within the tolerance range. However, this incurs a slight delay, as for
each mode, clk_round_rate() is called, which takes ~100 us. So, for a
monitor supporting 30 modes, it takes an extra 3.5 ms to do
clk_round_rate() to enumerate all modes. If the user wants to bypass
this validation logic, they can manually modify the driver to bypass
these calls selectively. For example, they can just do a
clk_round_rate() check for the highest resolution mode and bypass it
for the rest of the modes, as done here [1].

[1]: https://lore.kernel.org/all/20250704094851.182131-3-j-choudhary@ti.com/

Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support")
Tested-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Signed-off-by: Swamil Jain <s-jain1@ti.com>
---
 drivers/gpu/drm/tidss/tidss_dispc.c | 78 +++++++++++------------------
 drivers/gpu/drm/tidss/tidss_dispc.h |  1 -
 drivers/gpu/drm/tidss/tidss_drv.h   |  1 -
 3 files changed, 30 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index 7c8c15a5c39b..1cd83a6763ba 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -59,10 +59,6 @@ static const u16 tidss_k2g_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
 const struct dispc_features dispc_k2g_feats = {
 	.min_pclk_khz = 4375,
 
-	.max_pclk_khz = {
-		[DISPC_VP_DPI] = 150000,
-	},
-
 	/*
 	 * XXX According TRM the RGB input buffer width up to 2560 should
 	 *     work on 3 taps, but in practice it only works up to 1280.
@@ -145,11 +141,6 @@ static const u16 tidss_am65x_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
 };
 
 const struct dispc_features dispc_am65x_feats = {
-	.max_pclk_khz = {
-		[DISPC_VP_DPI] = 165000,
-		[DISPC_VP_OLDI_AM65X] = 165000,
-	},
-
 	.scaling = {
 		.in_width_max_5tap_rgb = 1280,
 		.in_width_max_3tap_rgb = 2560,
@@ -245,11 +236,6 @@ static const u16 tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
 };
 
 const struct dispc_features dispc_j721e_feats = {
-	.max_pclk_khz = {
-		[DISPC_VP_DPI] = 170000,
-		[DISPC_VP_INTERNAL] = 600000,
-	},
-
 	.scaling = {
 		.in_width_max_5tap_rgb = 2048,
 		.in_width_max_3tap_rgb = 4096,
@@ -316,11 +302,6 @@ const struct dispc_features dispc_j721e_feats = {
 };
 
 const struct dispc_features dispc_am625_feats = {
-	.max_pclk_khz = {
-		[DISPC_VP_DPI] = 165000,
-		[DISPC_VP_INTERNAL] = 170000,
-	},
-
 	.scaling = {
 		.in_width_max_5tap_rgb = 1280,
 		.in_width_max_3tap_rgb = 2560,
@@ -377,15 +358,6 @@ const struct dispc_features dispc_am625_feats = {
 };
 
 const struct dispc_features dispc_am62a7_feats = {
-	/*
-	 * if the code reaches dispc_mode_valid with VP1,
-	 * it should return MODE_BAD.
-	 */
-	.max_pclk_khz = {
-		[DISPC_VP_TIED_OFF] = 0,
-		[DISPC_VP_DPI] = 165000,
-	},
-
 	.scaling = {
 		.in_width_max_5tap_rgb = 1280,
 		.in_width_max_3tap_rgb = 2560,
@@ -442,10 +414,6 @@ const struct dispc_features dispc_am62a7_feats = {
 };
 
 const struct dispc_features dispc_am62l_feats = {
-	.max_pclk_khz = {
-		[DISPC_VP_DPI] = 165000,
-	},
-
 	.subrev = DISPC_AM62L,
 
 	.common = "common",
@@ -1331,25 +1299,50 @@ static void dispc_vp_set_default_color(struct dispc_device *dispc,
 			DISPC_OVR_DEFAULT_COLOR2, (v >> 32) & 0xffff);
 }
 
+/*
+ * Calculate the percentage difference between the requested pixel clock rate
+ * and the effective rate resulting from calculating the clock divider value.
+ */
+unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate)
+{
+	int r = rate / 100, rr = real_rate / 100;
+
+	return (unsigned int)(abs(((rr - r) * 100) / r));
+}
+
+static int check_pixel_clock(struct dispc_device *dispc,
+			     u32 hw_videoport, unsigned long clock)
+{
+	unsigned long round_clock;
+
+	if (dispc->tidss->is_ext_vp_clk[hw_videoport])
+		return 0;
+	round_clock = clk_round_rate(dispc->vp_clk[hw_videoport], clock);
+	/*
+	 * To keep the check consistent with dispc_vp_set_clk_rate(), we
+	 * use the same 5% check here.
+	 */
+	if (dispc_pclk_diff(clock, round_clock) > 5)
+		return -EINVAL;
+	return 0;
+}
+
 enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
 					 u32 hw_videoport,
 					 const struct drm_display_mode *mode)
 {
 	u32 hsw, hfp, hbp, vsw, vfp, vbp;
 	enum dispc_vp_bus_type bus_type;
-	int max_pclk;
 
 	bus_type = dispc->feat->vp_bus_type[hw_videoport];
 
-	max_pclk = dispc->feat->max_pclk_khz[bus_type];
-
-	if (WARN_ON(max_pclk == 0))
+	if (WARN_ON(bus_type == DISPC_VP_TIED_OFF))
 		return MODE_BAD;
 
 	if (mode->clock < dispc->feat->min_pclk_khz)
 		return MODE_CLOCK_LOW;
 
-	if (mode->clock > max_pclk)
+	if (check_pixel_clock(dispc, hw_videoport, mode->clock * 1000))
 		return MODE_CLOCK_HIGH;
 
 	if (mode->hdisplay > 4096)
@@ -1421,17 +1414,6 @@ void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport)
 	clk_disable_unprepare(dispc->vp_clk[hw_videoport]);
 }
 
-/*
- * Calculate the percentage difference between the requested pixel clock rate
- * and the effective rate resulting from calculating the clock divider value.
- */
-unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate)
-{
-	int r = rate / 100, rr = real_rate / 100;
-
-	return (unsigned int)(abs(((rr - r) * 100) / r));
-}
-
 int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
 			  unsigned long rate)
 {
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h
index 60c1b400eb89..fbfe6e304ac8 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.h
+++ b/drivers/gpu/drm/tidss/tidss_dispc.h
@@ -78,7 +78,6 @@ enum dispc_dss_subrevision {
 
 struct dispc_features {
 	int min_pclk_khz;
-	int max_pclk_khz[DISPC_VP_MAX_BUS_TYPE];
 
 	struct dispc_features_scaling scaling;
 
diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tidss_drv.h
index e1c1f41d8b4b..f82e282e17a7 100644
--- a/drivers/gpu/drm/tidss/tidss_drv.h
+++ b/drivers/gpu/drm/tidss/tidss_drv.h
@@ -26,7 +26,6 @@ struct tidss_device {
 	struct dispc_device *dispc;
 	bool is_ext_vp_clk[TIDSS_MAX_PORTS];
 
-
 	unsigned int num_crtcs;
 	struct drm_crtc *crtcs[TIDSS_MAX_PORTS];
 

[PATCH v6 3/3] drm/tidss: oldi: Add atomic_check hook for oldi bridge

[Swamil Jain]

From: Jayesh Choudhary <j-choudhary@ti.com>

Since OLDI consumes DSS VP clock directly as serial clock, mode_valid()
check cannot be performed in tidss driver which should be checked
in OLDI driver.

Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support")
Tested-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Signed-off-by: Swamil Jain <s-jain1@ti.com>
---
 drivers/gpu/drm/tidss/tidss_oldi.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/tidss/tidss_oldi.c
index 7ecbb2c3d0a2..ada691839ef3 100644
--- a/drivers/gpu/drm/tidss/tidss_oldi.c
+++ b/drivers/gpu/drm/tidss/tidss_oldi.c
@@ -309,6 +309,26 @@ static u32 *tidss_oldi_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
 	return input_fmts;
 }
 
+static int tidss_oldi_atomic_check(struct drm_bridge *bridge,
+				   struct drm_bridge_state *bridge_state,
+				   struct drm_crtc_state *crtc_state,
+				   struct drm_connector_state *conn_state)
+{
+	struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge);
+	struct drm_display_mode *adjusted_mode;
+	unsigned long round_clock;
+
+	adjusted_mode = &crtc_state->adjusted_mode;
+	round_clock = clk_round_rate(oldi->serial, adjusted_mode->clock * 7 * 1000);
+	/*
+	 * To keep the check consistent with dispc_vp_set_clk_rate(),
+	 * we use the same 5% check here.
+	 */
+	if (dispc_pclk_diff(adjusted_mode->clock * 7 * 1000, round_clock) > 5)
+		return -EINVAL;
+	return 0;
+}
+
 static const struct drm_bridge_funcs tidss_oldi_bridge_funcs = {
 	.attach	= tidss_oldi_bridge_attach,
 	.atomic_pre_enable = tidss_oldi_atomic_pre_enable,
@@ -317,6 +337,7 @@ static const struct drm_bridge_funcs tidss_oldi_bridge_funcs = {
 	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
 	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
 	.atomic_reset = drm_atomic_helper_bridge_reset,
+	.atomic_check = tidss_oldi_atomic_check,
 };
 
 static int get_oldi_mode(struct device_node *oldi_tx, int *companion_instance)

Re: [PATCH v6 3/3] drm/tidss: oldi: Add atomic_check hook for oldi bridge

[Maxime Ripard]

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On Thu, Sep 11, 2025 at 04:37:15PM +0530, Swamil Jain wrote:
> From: Jayesh Choudhary <j-choudhary@ti.com>
> 
> Since OLDI consumes DSS VP clock directly as serial clock, mode_valid()
> check cannot be performed in tidss driver which should be checked
> in OLDI driver.
> 
> Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support")
> Tested-by: Michael Walle <mwalle@kernel.org>
> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> Signed-off-by: Swamil Jain <s-jain1@ti.com>
> ---
>  drivers/gpu/drm/tidss/tidss_oldi.c | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/tidss/tidss_oldi.c
> index 7ecbb2c3d0a2..ada691839ef3 100644
> --- a/drivers/gpu/drm/tidss/tidss_oldi.c
> +++ b/drivers/gpu/drm/tidss/tidss_oldi.c
> @@ -309,6 +309,26 @@ static u32 *tidss_oldi_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
>  	return input_fmts;
>  }
>  
> +static int tidss_oldi_atomic_check(struct drm_bridge *bridge,
> +				   struct drm_bridge_state *bridge_state,
> +				   struct drm_crtc_state *crtc_state,
> +				   struct drm_connector_state *conn_state)
> +{
> +	struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge);
> +	struct drm_display_mode *adjusted_mode;
> +	unsigned long round_clock;
> +
> +	adjusted_mode = &crtc_state->adjusted_mode;
> +	round_clock = clk_round_rate(oldi->serial, adjusted_mode->clock * 7 * 1000);
> +	/*
> +	 * To keep the check consistent with dispc_vp_set_clk_rate(),
> +	 * we use the same 5% check here.
> +	 */
> +	if (dispc_pclk_diff(adjusted_mode->clock * 7 * 1000, round_clock) > 5)
> +		return -EINVAL;
> +	return 0;
> +}
> +

If you're introducing that check to tidss, please use .5% like everyone
else. I understand that you don't want to change tilcdc to avoid any
regression, but that's not the case here

Maxime

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Re: [PATCH v6 3/3] drm/tidss: oldi: Add atomic_check hook for oldi bridge

[Swamil Jain]

Hi,

On 9/15/25 13:27, Maxime Ripard wrote:
> On Thu, Sep 11, 2025 at 04:37:15PM +0530, Swamil Jain wrote:
>> From: Jayesh Choudhary <j-choudhary@ti.com>
>>
>> Since OLDI consumes DSS VP clock directly as serial clock, mode_valid()
>> check cannot be performed in tidss driver which should be checked
>> in OLDI driver.
>>
>> Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support")
>> Tested-by: Michael Walle <mwalle@kernel.org>
>> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>> Signed-off-by: Swamil Jain <s-jain1@ti.com>
>> ---
>>   drivers/gpu/drm/tidss/tidss_oldi.c | 21 +++++++++++++++++++++
>>   1 file changed, 21 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/tidss/tidss_oldi.c
>> index 7ecbb2c3d0a2..ada691839ef3 100644
>> --- a/drivers/gpu/drm/tidss/tidss_oldi.c
>> +++ b/drivers/gpu/drm/tidss/tidss_oldi.c
>> @@ -309,6 +309,26 @@ static u32 *tidss_oldi_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
>>   	return input_fmts;
>>   }
>>   
>> +static int tidss_oldi_atomic_check(struct drm_bridge *bridge,
>> +				   struct drm_bridge_state *bridge_state,
>> +				   struct drm_crtc_state *crtc_state,
>> +				   struct drm_connector_state *conn_state)
>> +{
>> +	struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge);
>> +	struct drm_display_mode *adjusted_mode;
>> +	unsigned long round_clock;
>> +
>> +	adjusted_mode = &crtc_state->adjusted_mode;
>> +	round_clock = clk_round_rate(oldi->serial, adjusted_mode->clock * 7 * 1000);
>> +	/*
>> +	 * To keep the check consistent with dispc_vp_set_clk_rate(),
>> +	 * we use the same 5% check here.
>> +	 */
>> +	if (dispc_pclk_diff(adjusted_mode->clock * 7 * 1000, round_clock) > 5)
>> +		return -EINVAL;
>> +	return 0;
>> +}
>> +
> 
> If you're introducing that check to tidss, please use .5% like everyone
> else. I understand that you don't want to change tilcdc to avoid any
> regression, but that's not the case here
>
This is just to make the tolerance check consistent for mode validation 
and setting clock rate. This patch isn't introducing anything new, we 
are following this as dispc_vp_set_clk_rate() and 
tidss_oldi_set_serial_clk() are already checking for 5% tolerance while 
setting clock. To remove/modify, this needs extensive testing with other 
K3 and K2G SoCs and can be handled as a separate patch.

Regards,
Swamil

> Maxime

Re: [PATCH v6 3/3] drm/tidss: oldi: Add atomic_check hook for oldi bridge

[Tomi Valkeinen]

Hi,

On 15/09/2025 11:55, Swamil Jain wrote:
> Hi,
> 
> On 9/15/25 13:27, Maxime Ripard wrote:
>> On Thu, Sep 11, 2025 at 04:37:15PM +0530, Swamil Jain wrote:
>>> From: Jayesh Choudhary <j-choudhary@ti.com>
>>>
>>> Since OLDI consumes DSS VP clock directly as serial clock, mode_valid()
>>> check cannot be performed in tidss driver which should be checked
>>> in OLDI driver.
>>>
>>> Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support")
>>> Tested-by: Michael Walle <mwalle@kernel.org>
>>> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
>>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>>> Signed-off-by: Swamil Jain <s-jain1@ti.com>
>>> ---
>>>   drivers/gpu/drm/tidss/tidss_oldi.c | 21 +++++++++++++++++++++
>>>   1 file changed, 21 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/
>>> tidss/tidss_oldi.c
>>> index 7ecbb2c3d0a2..ada691839ef3 100644
>>> --- a/drivers/gpu/drm/tidss/tidss_oldi.c
>>> +++ b/drivers/gpu/drm/tidss/tidss_oldi.c
>>> @@ -309,6 +309,26 @@ static u32
>>> *tidss_oldi_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
>>>       return input_fmts;
>>>   }
>>>   +static int tidss_oldi_atomic_check(struct drm_bridge *bridge,
>>> +                   struct drm_bridge_state *bridge_state,
>>> +                   struct drm_crtc_state *crtc_state,
>>> +                   struct drm_connector_state *conn_state)
>>> +{
>>> +    struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge);
>>> +    struct drm_display_mode *adjusted_mode;
>>> +    unsigned long round_clock;
>>> +
>>> +    adjusted_mode = &crtc_state->adjusted_mode;
>>> +    round_clock = clk_round_rate(oldi->serial, adjusted_mode->clock
>>> * 7 * 1000);
>>> +    /*
>>> +     * To keep the check consistent with dispc_vp_set_clk_rate(),
>>> +     * we use the same 5% check here.
>>> +     */
>>> +    if (dispc_pclk_diff(adjusted_mode->clock * 7 * 1000,
>>> round_clock) > 5)
>>> +        return -EINVAL;
>>> +    return 0;
>>> +}
>>> +
>>
>> If you're introducing that check to tidss, please use .5% like everyone
>> else. I understand that you don't want to change tilcdc to avoid any
>> regression, but that's not the case here
>>
> This is just to make the tolerance check consistent for mode validation
> and setting clock rate. This patch isn't introducing anything new, we
> are following this as dispc_vp_set_clk_rate() and
> tidss_oldi_set_serial_clk() are already checking for 5% tolerance while
> setting clock. To remove/modify, this needs extensive testing with other
> K3 and K2G SoCs and can be handled as a separate patch.

I'd like to switch to 0.5%, but as Swamil said, I think it's better to
do it on top.

 Tomi

Re: [PATCH v6 3/3] drm/tidss: oldi: Add atomic_check hook for oldi bridge

[Maxime Ripard]

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On Mon, Sep 15, 2025 at 01:17:52PM +0300, Tomi Valkeinen wrote:
> Hi,
> 
> On 15/09/2025 11:55, Swamil Jain wrote:
> > Hi,
> > 
> > On 9/15/25 13:27, Maxime Ripard wrote:
> >> On Thu, Sep 11, 2025 at 04:37:15PM +0530, Swamil Jain wrote:
> >>> From: Jayesh Choudhary <j-choudhary@ti.com>
> >>>
> >>> Since OLDI consumes DSS VP clock directly as serial clock, mode_valid()
> >>> check cannot be performed in tidss driver which should be checked
> >>> in OLDI driver.
> >>>
> >>> Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support")
> >>> Tested-by: Michael Walle <mwalle@kernel.org>
> >>> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
> >>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> >>> Signed-off-by: Swamil Jain <s-jain1@ti.com>
> >>> ---
> >>>   drivers/gpu/drm/tidss/tidss_oldi.c | 21 +++++++++++++++++++++
> >>>   1 file changed, 21 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/
> >>> tidss/tidss_oldi.c
> >>> index 7ecbb2c3d0a2..ada691839ef3 100644
> >>> --- a/drivers/gpu/drm/tidss/tidss_oldi.c
> >>> +++ b/drivers/gpu/drm/tidss/tidss_oldi.c
> >>> @@ -309,6 +309,26 @@ static u32
> >>> *tidss_oldi_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
> >>>       return input_fmts;
> >>>   }
> >>>   +static int tidss_oldi_atomic_check(struct drm_bridge *bridge,
> >>> +                   struct drm_bridge_state *bridge_state,
> >>> +                   struct drm_crtc_state *crtc_state,
> >>> +                   struct drm_connector_state *conn_state)
> >>> +{
> >>> +    struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge);
> >>> +    struct drm_display_mode *adjusted_mode;
> >>> +    unsigned long round_clock;
> >>> +
> >>> +    adjusted_mode = &crtc_state->adjusted_mode;
> >>> +    round_clock = clk_round_rate(oldi->serial, adjusted_mode->clock
> >>> * 7 * 1000);
> >>> +    /*
> >>> +     * To keep the check consistent with dispc_vp_set_clk_rate(),
> >>> +     * we use the same 5% check here.
> >>> +     */
> >>> +    if (dispc_pclk_diff(adjusted_mode->clock * 7 * 1000,
> >>> round_clock) > 5)
> >>> +        return -EINVAL;
> >>> +    return 0;
> >>> +}
> >>> +
> >>
> >> If you're introducing that check to tidss, please use .5% like everyone
> >> else. I understand that you don't want to change tilcdc to avoid any
> >> regression, but that's not the case here
> >>
> > This is just to make the tolerance check consistent for mode validation
> > and setting clock rate. This patch isn't introducing anything new, we
> > are following this as dispc_vp_set_clk_rate() and
> > tidss_oldi_set_serial_clk() are already checking for 5% tolerance while
> > setting clock. To remove/modify, this needs extensive testing with other
> > K3 and K2G SoCs and can be handled as a separate patch.
> 
> I'd like to switch to 0.5%, but as Swamil said, I think it's better to
> do it on top.

Yeah, sorry, I thought it was a new thing.

Maxime

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Re: [PATCH v6 1/3] drm/tidss: oldi: Add property to identify OLDI supported VP

[Tomi Valkeinen]

Hi,

On 11/09/2025 14:07, Swamil Jain wrote:
> From: Jayesh Choudhary <j-choudhary@ti.com>
> 
> TIDSS should know which VP has OLDI output to avoid calling clock
> functions for that VP as those are controlled by oldi driver. Add a
> property "is_ext_vp_clk" to "tidss_device" structure for that. Mark it
> 'true' in tidss_oldi_init() and 'false' in tidss_oldi_deinit().
> 
> Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support")

What bug does this fix? It's just adding a new field which it sets to
true/false...

 Tomi

> Tested-by: Michael Walle <mwalle@kernel.org>
> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> Signed-off-by: Swamil Jain <s-jain1@ti.com>
> ---
>  drivers/gpu/drm/tidss/tidss_drv.h  | 2 ++
>  drivers/gpu/drm/tidss/tidss_oldi.c | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tidss_drv.h
> index 84454a4855d1..e1c1f41d8b4b 100644
> --- a/drivers/gpu/drm/tidss/tidss_drv.h
> +++ b/drivers/gpu/drm/tidss/tidss_drv.h
> @@ -24,6 +24,8 @@ struct tidss_device {
>  
>  	const struct dispc_features *feat;
>  	struct dispc_device *dispc;
> +	bool is_ext_vp_clk[TIDSS_MAX_PORTS];
> +
>  
>  	unsigned int num_crtcs;
>  	struct drm_crtc *crtcs[TIDSS_MAX_PORTS];
> diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/tidss/tidss_oldi.c
> index 7688251beba2..7ecbb2c3d0a2 100644
> --- a/drivers/gpu/drm/tidss/tidss_oldi.c
> +++ b/drivers/gpu/drm/tidss/tidss_oldi.c
> @@ -430,6 +430,7 @@ void tidss_oldi_deinit(struct tidss_device *tidss)
>  	for (int i = 0; i < tidss->num_oldis; i++) {
>  		if (tidss->oldis[i]) {
>  			drm_bridge_remove(&tidss->oldis[i]->bridge);
> +			tidss->is_ext_vp_clk[tidss->oldis[i]->parent_vp] = false;
>  			tidss->oldis[i] = NULL;
>  		}
>  	}
> @@ -580,6 +581,7 @@ int tidss_oldi_init(struct tidss_device *tidss)
>  		oldi->bridge.timings = &default_tidss_oldi_timings;
>  
>  		tidss->oldis[tidss->num_oldis++] = oldi;
> +		tidss->is_ext_vp_clk[oldi->parent_vp] = true;
>  		oldi->tidss = tidss;
>  
>  		drm_bridge_add(&oldi->bridge);

Re: [PATCH v6 2/3] drm/tidss: Remove max_pclk_khz from tidss display features:

[Tomi Valkeinen]

Hi,

On 11/09/2025 14:07, Swamil Jain wrote:
> From: Jayesh Choudhary <j-choudhary@ti.com>
> 
> TIDSS hardware, by itself, does not have variable max pixel clock for
> each VP. The maximum pixel clock is determined by the SoC's clocking
> architecture.
> 
> The limitation that has been modeled until now comes from the SoC's
> clocking architecture (PLL can only be programmed to a particular max
> value). Instead of putting it as a constant field in dispc_features,
> we can use clk_round_rate() to see if requested clock can be set or not.
> 
> Remove the constant "max_pclk_khz" from dispc_features. In mode_valid()
> call, check if a best frequency match for the mode clock can be found
> or not using clk_round_rate().
> 
> Since TIDSS display controller provides clock tolerance of 5%, we use
> this while checking if the requested pixel clock is supported. Also,
> move up dispc_pclk_diff() before it is called.

I think in the next version you could add a patch on top which changes
the limit to 0.5% as discussed.

> This will make the existing compatibles reusable if DSS features are
> the same across two SoCs with the only difference being the pixel clock.
> 
> Note:
> This uses clk_round_rate() to validate all modes and ensure that the
> driver enumerates only those whose clocking requirements are well
> within the tolerance range. However, this incurs a slight delay, as for
> each mode, clk_round_rate() is called, which takes ~100 us. So, for a
> monitor supporting 30 modes, it takes an extra 3.5 ms to do
> clk_round_rate() to enumerate all modes. If the user wants to bypass
> this validation logic, they can manually modify the driver to bypass
> these calls selectively. For example, they can just do a
> clk_round_rate() check for the highest resolution mode and bypass it
> for the rest of the modes, as done here [1].

A more important topic to cover in the description is the change of
behavior: does the driver behave differently now, and how?

I think there's a chance that this change produces issues, but if that
realized we need to deal with them by some other way than having the
max-pclk in dispc. The possible issue is that e.g. SoC's DPI output has
limitations on how fast the clock can be. So the PLL could go up to,
say, 600 MHz, and DSS could do that, but the DPI path would probably
have trouble somewhere around 200-300MHz. Now, there's a good chance
that the DPI peripheral (panel, bridge) will already limit the pclk. But
if not, we might get into a case where tidss driver thinks the clock is
fine, but the SoC can't really output that via DPI.

> [1]: https://lore.kernel.org/all/20250704094851.182131-3-j-choudhary@ti.com/
> 
> Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support")

What bug does this fix?

> Tested-by: Michael Walle <mwalle@kernel.org>
> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> Signed-off-by: Swamil Jain <s-jain1@ti.com>
> ---
>  drivers/gpu/drm/tidss/tidss_dispc.c | 78 +++++++++++------------------
>  drivers/gpu/drm/tidss/tidss_dispc.h |  1 -
>  drivers/gpu/drm/tidss/tidss_drv.h   |  1 -
>  3 files changed, 30 insertions(+), 50 deletions(-)
> 
> diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
> index 7c8c15a5c39b..1cd83a6763ba 100644
> --- a/drivers/gpu/drm/tidss/tidss_dispc.c
> +++ b/drivers/gpu/drm/tidss/tidss_dispc.c
> @@ -59,10 +59,6 @@ static const u16 tidss_k2g_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
>  const struct dispc_features dispc_k2g_feats = {
>  	.min_pclk_khz = 4375,
>  
> -	.max_pclk_khz = {
> -		[DISPC_VP_DPI] = 150000,
> -	},
> -
>  	/*
>  	 * XXX According TRM the RGB input buffer width up to 2560 should
>  	 *     work on 3 taps, but in practice it only works up to 1280.
> @@ -145,11 +141,6 @@ static const u16 tidss_am65x_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
>  };
>  
>  const struct dispc_features dispc_am65x_feats = {
> -	.max_pclk_khz = {
> -		[DISPC_VP_DPI] = 165000,
> -		[DISPC_VP_OLDI_AM65X] = 165000,
> -	},
> -
>  	.scaling = {
>  		.in_width_max_5tap_rgb = 1280,
>  		.in_width_max_3tap_rgb = 2560,
> @@ -245,11 +236,6 @@ static const u16 tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
>  };
>  
>  const struct dispc_features dispc_j721e_feats = {
> -	.max_pclk_khz = {
> -		[DISPC_VP_DPI] = 170000,
> -		[DISPC_VP_INTERNAL] = 600000,
> -	},
> -
>  	.scaling = {
>  		.in_width_max_5tap_rgb = 2048,
>  		.in_width_max_3tap_rgb = 4096,
> @@ -316,11 +302,6 @@ const struct dispc_features dispc_j721e_feats = {
>  };
>  
>  const struct dispc_features dispc_am625_feats = {
> -	.max_pclk_khz = {
> -		[DISPC_VP_DPI] = 165000,
> -		[DISPC_VP_INTERNAL] = 170000,
> -	},
> -
>  	.scaling = {
>  		.in_width_max_5tap_rgb = 1280,
>  		.in_width_max_3tap_rgb = 2560,
> @@ -377,15 +358,6 @@ const struct dispc_features dispc_am625_feats = {
>  };
>  
>  const struct dispc_features dispc_am62a7_feats = {
> -	/*
> -	 * if the code reaches dispc_mode_valid with VP1,
> -	 * it should return MODE_BAD.
> -	 */
> -	.max_pclk_khz = {
> -		[DISPC_VP_TIED_OFF] = 0,
> -		[DISPC_VP_DPI] = 165000,
> -	},
> -
>  	.scaling = {
>  		.in_width_max_5tap_rgb = 1280,
>  		.in_width_max_3tap_rgb = 2560,
> @@ -442,10 +414,6 @@ const struct dispc_features dispc_am62a7_feats = {
>  };
>  
>  const struct dispc_features dispc_am62l_feats = {
> -	.max_pclk_khz = {
> -		[DISPC_VP_DPI] = 165000,
> -	},
> -
>  	.subrev = DISPC_AM62L,
>  
>  	.common = "common",
> @@ -1331,25 +1299,50 @@ static void dispc_vp_set_default_color(struct dispc_device *dispc,
>  			DISPC_OVR_DEFAULT_COLOR2, (v >> 32) & 0xffff);
>  }
>  
> +/*
> + * Calculate the percentage difference between the requested pixel clock rate
> + * and the effective rate resulting from calculating the clock divider value.
> + */
> +unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate)
> +{
> +	int r = rate / 100, rr = real_rate / 100;
> +
> +	return (unsigned int)(abs(((rr - r) * 100) / r));
> +}
> +
> +static int check_pixel_clock(struct dispc_device *dispc,
> +			     u32 hw_videoport, unsigned long clock)
> +{
> +	unsigned long round_clock;
> +
> +	if (dispc->tidss->is_ext_vp_clk[hw_videoport])
> +		return 0;
> +	round_clock = clk_round_rate(dispc->vp_clk[hw_videoport], clock);
> +	/*
> +	 * To keep the check consistent with dispc_vp_set_clk_rate(), we
> +	 * use the same 5% check here.
> +	 */

This is fine for now, but I think we need to revisit this in a future
patch. We should check the clock here in mode_valid, but also in
atomic_check. The clock we finally set in dispc_vp_set_clk_rate() should
be a "rounded" rate, know to work.

> +	if (dispc_pclk_diff(clock, round_clock) > 5)
> +		return -EINVAL;
> +	return 0;
> +}
> +
>  enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
>  					 u32 hw_videoport,
>  					 const struct drm_display_mode *mode)
>  {
>  	u32 hsw, hfp, hbp, vsw, vfp, vbp;
>  	enum dispc_vp_bus_type bus_type;
> -	int max_pclk;
>  
>  	bus_type = dispc->feat->vp_bus_type[hw_videoport];
>  
> -	max_pclk = dispc->feat->max_pclk_khz[bus_type];
> -
> -	if (WARN_ON(max_pclk == 0))
> +	if (WARN_ON(bus_type == DISPC_VP_TIED_OFF))
>  		return MODE_BAD;
>  
>  	if (mode->clock < dispc->feat->min_pclk_khz)
>  		return MODE_CLOCK_LOW;
>  
> -	if (mode->clock > max_pclk)
> +	if (check_pixel_clock(dispc, hw_videoport, mode->clock * 1000))
>  		return MODE_CLOCK_HIGH;

I think you can just inline check_pixel_clock() here, and return
MODE_CLOCK_HIGH or MODE_CLOCK_LOW depending on the rounded rate.

 Tomi

>  
>  	if (mode->hdisplay > 4096)
> @@ -1421,17 +1414,6 @@ void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport)
>  	clk_disable_unprepare(dispc->vp_clk[hw_videoport]);
>  }
>  
> -/*
> - * Calculate the percentage difference between the requested pixel clock rate
> - * and the effective rate resulting from calculating the clock divider value.
> - */
> -unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate)
> -{
> -	int r = rate / 100, rr = real_rate / 100;
> -
> -	return (unsigned int)(abs(((rr - r) * 100) / r));
> -}
> -
>  int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
>  			  unsigned long rate)
>  {
> diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h
> index 60c1b400eb89..fbfe6e304ac8 100644
> --- a/drivers/gpu/drm/tidss/tidss_dispc.h
> +++ b/drivers/gpu/drm/tidss/tidss_dispc.h
> @@ -78,7 +78,6 @@ enum dispc_dss_subrevision {
>  
>  struct dispc_features {
>  	int min_pclk_khz;
> -	int max_pclk_khz[DISPC_VP_MAX_BUS_TYPE];
>  
>  	struct dispc_features_scaling scaling;
>  
> diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tidss_drv.h
> index e1c1f41d8b4b..f82e282e17a7 100644
> --- a/drivers/gpu/drm/tidss/tidss_drv.h
> +++ b/drivers/gpu/drm/tidss/tidss_drv.h
> @@ -26,7 +26,6 @@ struct tidss_device {
>  	struct dispc_device *dispc;
>  	bool is_ext_vp_clk[TIDSS_MAX_PORTS];
>  
> -
>  	unsigned int num_crtcs;
>  	struct drm_crtc *crtcs[TIDSS_MAX_PORTS];
>  

Re: [PATCH v6 2/3] drm/tidss: Remove max_pclk_khz from tidss display features:

[Tomi Valkeinen]

Hi,

On 11/09/2025 14:07, Swamil Jain wrote:
> From: Jayesh Choudhary <j-choudhary@ti.com>
> 
> TIDSS hardware, by itself, does not have variable max pixel clock for
> each VP. The maximum pixel clock is determined by the SoC's clocking
> architecture.
> 
> The limitation that has been modeled until now comes from the SoC's
> clocking architecture (PLL can only be programmed to a particular max
> value). Instead of putting it as a constant field in dispc_features,
> we can use clk_round_rate() to see if requested clock can be set or not.
> 
> Remove the constant "max_pclk_khz" from dispc_features. In mode_valid()
> call, check if a best frequency match for the mode clock can be found
> or not using clk_round_rate().
> 
> Since TIDSS display controller provides clock tolerance of 5%, we use
> this while checking if the requested pixel clock is supported. Also,
> move up dispc_pclk_diff() before it is called.
> 
> This will make the existing compatibles reusable if DSS features are
> the same across two SoCs with the only difference being the pixel clock.
> 
> Note:
> This uses clk_round_rate() to validate all modes and ensure that the
> driver enumerates only those whose clocking requirements are well
> within the tolerance range. However, this incurs a slight delay, as for
> each mode, clk_round_rate() is called, which takes ~100 us. So, for a
> monitor supporting 30 modes, it takes an extra 3.5 ms to do
> clk_round_rate() to enumerate all modes. If the user wants to bypass
> this validation logic, they can manually modify the driver to bypass
> these calls selectively. For example, they can just do a
> clk_round_rate() check for the highest resolution mode and bypass it
> for the rest of the modes, as done here [1].
> 
> [1]: https://lore.kernel.org/all/20250704094851.182131-3-j-choudhary@ti.com/
> 
> Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support")
> Tested-by: Michael Walle <mwalle@kernel.org>
> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> Signed-off-by: Swamil Jain <s-jain1@ti.com>
> ---
>  drivers/gpu/drm/tidss/tidss_dispc.c | 78 +++++++++++------------------
>  drivers/gpu/drm/tidss/tidss_dispc.h |  1 -
>  drivers/gpu/drm/tidss/tidss_drv.h   |  1 -
>  3 files changed, 30 insertions(+), 50 deletions(-)
> 
> diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
> index 7c8c15a5c39b..1cd83a6763ba 100644
> --- a/drivers/gpu/drm/tidss/tidss_dispc.c
> +++ b/drivers/gpu/drm/tidss/tidss_dispc.c
> @@ -59,10 +59,6 @@ static const u16 tidss_k2g_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
>  const struct dispc_features dispc_k2g_feats = {
>  	.min_pclk_khz = 4375,
>  
> -	.max_pclk_khz = {
> -		[DISPC_VP_DPI] = 150000,
> -	},
> -
>  	/*
>  	 * XXX According TRM the RGB input buffer width up to 2560 should
>  	 *     work on 3 taps, but in practice it only works up to 1280.
> @@ -145,11 +141,6 @@ static const u16 tidss_am65x_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
>  };
>  
>  const struct dispc_features dispc_am65x_feats = {
> -	.max_pclk_khz = {
> -		[DISPC_VP_DPI] = 165000,
> -		[DISPC_VP_OLDI_AM65X] = 165000,
> -	},
> -
>  	.scaling = {
>  		.in_width_max_5tap_rgb = 1280,
>  		.in_width_max_3tap_rgb = 2560,
> @@ -245,11 +236,6 @@ static const u16 tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] = {
>  };
>  
>  const struct dispc_features dispc_j721e_feats = {
> -	.max_pclk_khz = {
> -		[DISPC_VP_DPI] = 170000,
> -		[DISPC_VP_INTERNAL] = 600000,
> -	},
> -
>  	.scaling = {
>  		.in_width_max_5tap_rgb = 2048,
>  		.in_width_max_3tap_rgb = 4096,
> @@ -316,11 +302,6 @@ const struct dispc_features dispc_j721e_feats = {
>  };
>  
>  const struct dispc_features dispc_am625_feats = {
> -	.max_pclk_khz = {
> -		[DISPC_VP_DPI] = 165000,
> -		[DISPC_VP_INTERNAL] = 170000,
> -	},
> -
>  	.scaling = {
>  		.in_width_max_5tap_rgb = 1280,
>  		.in_width_max_3tap_rgb = 2560,
> @@ -377,15 +358,6 @@ const struct dispc_features dispc_am625_feats = {
>  };
>  
>  const struct dispc_features dispc_am62a7_feats = {
> -	/*
> -	 * if the code reaches dispc_mode_valid with VP1,
> -	 * it should return MODE_BAD.
> -	 */
> -	.max_pclk_khz = {
> -		[DISPC_VP_TIED_OFF] = 0,
> -		[DISPC_VP_DPI] = 165000,
> -	},
> -
>  	.scaling = {
>  		.in_width_max_5tap_rgb = 1280,
>  		.in_width_max_3tap_rgb = 2560,
> @@ -442,10 +414,6 @@ const struct dispc_features dispc_am62a7_feats = {
>  };
>  
>  const struct dispc_features dispc_am62l_feats = {
> -	.max_pclk_khz = {
> -		[DISPC_VP_DPI] = 165000,
> -	},
> -
>  	.subrev = DISPC_AM62L,
>  
>  	.common = "common",
> @@ -1331,25 +1299,50 @@ static void dispc_vp_set_default_color(struct dispc_device *dispc,
>  			DISPC_OVR_DEFAULT_COLOR2, (v >> 32) & 0xffff);
>  }
>  
> +/*
> + * Calculate the percentage difference between the requested pixel clock rate
> + * and the effective rate resulting from calculating the clock divider value.
> + */
> +unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate)
> +{
> +	int r = rate / 100, rr = real_rate / 100;
> +
> +	return (unsigned int)(abs(((rr - r) * 100) / r));
> +}
> +
> +static int check_pixel_clock(struct dispc_device *dispc,
> +			     u32 hw_videoport, unsigned long clock)
> +{
> +	unsigned long round_clock;
> +
> +	if (dispc->tidss->is_ext_vp_clk[hw_videoport])
> +		return 0;
> +	round_clock = clk_round_rate(dispc->vp_clk[hw_videoport], clock);
> +	/*
> +	 * To keep the check consistent with dispc_vp_set_clk_rate(), we
> +	 * use the same 5% check here.
> +	 */
> +	if (dispc_pclk_diff(clock, round_clock) > 5)
> +		return -EINVAL;
> +	return 0;
> +}
> +
>  enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
>  					 u32 hw_videoport,
>  					 const struct drm_display_mode *mode)
>  {
>  	u32 hsw, hfp, hbp, vsw, vfp, vbp;
>  	enum dispc_vp_bus_type bus_type;
> -	int max_pclk;
>  
>  	bus_type = dispc->feat->vp_bus_type[hw_videoport];
>  
> -	max_pclk = dispc->feat->max_pclk_khz[bus_type];
> -
> -	if (WARN_ON(max_pclk == 0))
> +	if (WARN_ON(bus_type == DISPC_VP_TIED_OFF))
>  		return MODE_BAD;
>  
>  	if (mode->clock < dispc->feat->min_pclk_khz)
>  		return MODE_CLOCK_LOW;
>  

Shouldn't we drop the min_pclk_khz too?

 Tomi


> -	if (mode->clock > max_pclk)
> +	if (check_pixel_clock(dispc, hw_videoport, mode->clock * 1000))
>  		return MODE_CLOCK_HIGH;
>  
>  	if (mode->hdisplay > 4096)
> @@ -1421,17 +1414,6 @@ void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport)
>  	clk_disable_unprepare(dispc->vp_clk[hw_videoport]);
>  }
>  
> -/*
> - * Calculate the percentage difference between the requested pixel clock rate
> - * and the effective rate resulting from calculating the clock divider value.
> - */
> -unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate)
> -{
> -	int r = rate / 100, rr = real_rate / 100;
> -
> -	return (unsigned int)(abs(((rr - r) * 100) / r));
> -}
> -
>  int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
>  			  unsigned long rate)
>  {
> diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h
> index 60c1b400eb89..fbfe6e304ac8 100644
> --- a/drivers/gpu/drm/tidss/tidss_dispc.h
> +++ b/drivers/gpu/drm/tidss/tidss_dispc.h
> @@ -78,7 +78,6 @@ enum dispc_dss_subrevision {
>  
>  struct dispc_features {
>  	int min_pclk_khz;
> -	int max_pclk_khz[DISPC_VP_MAX_BUS_TYPE];
>  
>  	struct dispc_features_scaling scaling;
>  
> diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tidss_drv.h
> index e1c1f41d8b4b..f82e282e17a7 100644
> --- a/drivers/gpu/drm/tidss/tidss_drv.h
> +++ b/drivers/gpu/drm/tidss/tidss_drv.h
> @@ -26,7 +26,6 @@ struct tidss_device {
>  	struct dispc_device *dispc;
>  	bool is_ext_vp_clk[TIDSS_MAX_PORTS];
>  
> -
>  	unsigned int num_crtcs;
>  	struct drm_crtc *crtcs[TIDSS_MAX_PORTS];
>  

Re: [PATCH v6 3/3] drm/tidss: oldi: Add atomic_check hook for oldi bridge

[Tomi Valkeinen]

Hi,

On 11/09/2025 14:07, Swamil Jain wrote:
> From: Jayesh Choudhary <j-choudhary@ti.com>
> 
> Since OLDI consumes DSS VP clock directly as serial clock, mode_valid()
> check cannot be performed in tidss driver which should be checked
> in OLDI driver.

Please explain here a bit more what's going on here. You say
mode_valid() cannot be done in tidss. Why not? Then you add atomic_check
to oldi driver here, why is that the same as model_valid in tidss?

> Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support")

What bug does this fix?

> Tested-by: Michael Walle <mwalle@kernel.org>
> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> Signed-off-by: Swamil Jain <s-jain1@ti.com>
> ---
>  drivers/gpu/drm/tidss/tidss_oldi.c | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/tidss/tidss_oldi.c
> index 7ecbb2c3d0a2..ada691839ef3 100644
> --- a/drivers/gpu/drm/tidss/tidss_oldi.c
> +++ b/drivers/gpu/drm/tidss/tidss_oldi.c
> @@ -309,6 +309,26 @@ static u32 *tidss_oldi_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
>  	return input_fmts;
>  }
>  
> +static int tidss_oldi_atomic_check(struct drm_bridge *bridge,
> +				   struct drm_bridge_state *bridge_state,
> +				   struct drm_crtc_state *crtc_state,
> +				   struct drm_connector_state *conn_state)
> +{
> +	struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge);
> +	struct drm_display_mode *adjusted_mode;
> +	unsigned long round_clock;
> +
> +	adjusted_mode = &crtc_state->adjusted_mode;
> +	round_clock = clk_round_rate(oldi->serial, adjusted_mode->clock * 7 * 1000);
> +	/*
> +	 * To keep the check consistent with dispc_vp_set_clk_rate(),
> +	 * we use the same 5% check here.
> +	 */
> +	if (dispc_pclk_diff(adjusted_mode->clock * 7 * 1000, round_clock) > 5)
> +		return -EINVAL;
> +	return 0;
> +}
> +
>  static const struct drm_bridge_funcs tidss_oldi_bridge_funcs = {
>  	.attach	= tidss_oldi_bridge_attach,
>  	.atomic_pre_enable = tidss_oldi_atomic_pre_enable,
> @@ -317,6 +337,7 @@ static const struct drm_bridge_funcs tidss_oldi_bridge_funcs = {
>  	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
>  	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
>  	.atomic_reset = drm_atomic_helper_bridge_reset,
> +	.atomic_check = tidss_oldi_atomic_check,
>  };
>  
>  static int get_oldi_mode(struct device_node *oldi_tx, int *companion_instance)

Re: [PATCH v6 1/3] drm/tidss: oldi: Add property to identify OLDI supported VP

[Swamil Jain]

Hi Tomi,

On 9/16/25 17:10, Tomi Valkeinen wrote:
> Hi,
> 
> On 11/09/2025 14:07, Swamil Jain wrote:
>> From: Jayesh Choudhary <j-choudhary@ti.com>
>>
>> TIDSS should know which VP has OLDI output to avoid calling clock
>> functions for that VP as those are controlled by oldi driver. Add a
>> property "is_ext_vp_clk" to "tidss_device" structure for that. Mark it
>> 'true' in tidss_oldi_init() and 'false' in tidss_oldi_deinit().
>>
>> Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support")
> 
> What bug does this fix? It's just adding a new field which it sets to
> true/false...

Please take a look: 
https://lore.kernel.org/all/a0489fea-8c06-4c89-a530-8be691f4705d@ti.com/

Should we remove the tag?
Or, else, please suggest a better way to describe the issue mentioned in 
above link.

Regards,
Swamil
> 
>   Tomi
> 
>> Tested-by: Michael Walle <mwalle@kernel.org>
>> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>> Signed-off-by: Swamil Jain <s-jain1@ti.com>
>> ---
>>   drivers/gpu/drm/tidss/tidss_drv.h  | 2 ++
>>   drivers/gpu/drm/tidss/tidss_oldi.c | 2 ++
>>   2 files changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tidss_drv.h
>> index 84454a4855d1..e1c1f41d8b4b 100644
>> --- a/drivers/gpu/drm/tidss/tidss_drv.h
>> +++ b/drivers/gpu/drm/tidss/tidss_drv.h
>> @@ -24,6 +24,8 @@ struct tidss_device {
>>   
>>   	const struct dispc_features *feat;
>>   	struct dispc_device *dispc;
>> +	bool is_ext_vp_clk[TIDSS_MAX_PORTS];
>> +
>>   
>>   	unsigned int num_crtcs;
>>   	struct drm_crtc *crtcs[TIDSS_MAX_PORTS];
>> diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/tidss/tidss_oldi.c
>> index 7688251beba2..7ecbb2c3d0a2 100644
>> --- a/drivers/gpu/drm/tidss/tidss_oldi.c
>> +++ b/drivers/gpu/drm/tidss/tidss_oldi.c
>> @@ -430,6 +430,7 @@ void tidss_oldi_deinit(struct tidss_device *tidss)
>>   	for (int i = 0; i < tidss->num_oldis; i++) {
>>   		if (tidss->oldis[i]) {
>>   			drm_bridge_remove(&tidss->oldis[i]->bridge);
>> +			tidss->is_ext_vp_clk[tidss->oldis[i]->parent_vp] = false;
>>   			tidss->oldis[i] = NULL;
>>   		}
>>   	}
>> @@ -580,6 +581,7 @@ int tidss_oldi_init(struct tidss_device *tidss)
>>   		oldi->bridge.timings = &default_tidss_oldi_timings;
>>   
>>   		tidss->oldis[tidss->num_oldis++] = oldi;
>> +		tidss->is_ext_vp_clk[oldi->parent_vp] = true;
>>   		oldi->tidss = tidss;
>>   
>>   		drm_bridge_add(&oldi->bridge);
> 

Re: [PATCH v6 1/3] drm/tidss: oldi: Add property to identify OLDI supported VP

[Tomi Valkeinen]

Hi,

On 17/09/2025 16:32, Swamil Jain wrote:
> Hi Tomi,
> 
> On 9/16/25 17:10, Tomi Valkeinen wrote:
>> Hi,
>>
>> On 11/09/2025 14:07, Swamil Jain wrote:
>>> From: Jayesh Choudhary <j-choudhary@ti.com>
>>>
>>> TIDSS should know which VP has OLDI output to avoid calling clock
>>> functions for that VP as those are controlled by oldi driver. Add a
>>> property "is_ext_vp_clk" to "tidss_device" structure for that. Mark it
>>> 'true' in tidss_oldi_init() and 'false' in tidss_oldi_deinit().
>>>
>>> Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support")
>>
>> What bug does this fix? It's just adding a new field which it sets to
>> true/false...
> 
> Please take a look: https://lore.kernel.org/all/a0489fea-8c06-4c89-
> a530-8be691f4705d@ti.com/

There isn't a mention of any issue or fix in the intro letter nor the
patch descriptions, so a fixes tag looks very odd here.

Usually a Fixes tag is for a patch that does the fix. And, of course,
explains what the issue is and what the fix is.

If I understand this right, the fix is this from the patch 2:

+	if (dispc->tidss->is_ext_vp_clk[hw_videoport])
+		return 0;

And patch 3?

Those should be probably made into a single patch that fixes the issue.

Also, bridges have mode_valid callback. Would that be better in patch 3?

 Tomi

> Should we remove the tag?
> Or, else, please suggest a better way to describe the issue mentioned in
> above link.
> 
> Regards,
> Swamil
>>
>>   Tomi
>>
>>> Tested-by: Michael Walle <mwalle@kernel.org>
>>> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
>>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>>> Signed-off-by: Swamil Jain <s-jain1@ti.com>
>>> ---
>>>   drivers/gpu/drm/tidss/tidss_drv.h  | 2 ++
>>>   drivers/gpu/drm/tidss/tidss_oldi.c | 2 ++
>>>   2 files changed, 4 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/
>>> tidss/tidss_drv.h
>>> index 84454a4855d1..e1c1f41d8b4b 100644
>>> --- a/drivers/gpu/drm/tidss/tidss_drv.h
>>> +++ b/drivers/gpu/drm/tidss/tidss_drv.h
>>> @@ -24,6 +24,8 @@ struct tidss_device {
>>>         const struct dispc_features *feat;
>>>       struct dispc_device *dispc;
>>> +    bool is_ext_vp_clk[TIDSS_MAX_PORTS];
>>> +
>>>         unsigned int num_crtcs;
>>>       struct drm_crtc *crtcs[TIDSS_MAX_PORTS];
>>> diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/
>>> tidss/tidss_oldi.c
>>> index 7688251beba2..7ecbb2c3d0a2 100644
>>> --- a/drivers/gpu/drm/tidss/tidss_oldi.c
>>> +++ b/drivers/gpu/drm/tidss/tidss_oldi.c
>>> @@ -430,6 +430,7 @@ void tidss_oldi_deinit(struct tidss_device *tidss)
>>>       for (int i = 0; i < tidss->num_oldis; i++) {
>>>           if (tidss->oldis[i]) {
>>>               drm_bridge_remove(&tidss->oldis[i]->bridge);
>>> +            tidss->is_ext_vp_clk[tidss->oldis[i]->parent_vp] = false;
>>>               tidss->oldis[i] = NULL;
>>>           }
>>>       }
>>> @@ -580,6 +581,7 @@ int tidss_oldi_init(struct tidss_device *tidss)
>>>           oldi->bridge.timings = &default_tidss_oldi_timings;
>>>             tidss->oldis[tidss->num_oldis++] = oldi;
>>> +        tidss->is_ext_vp_clk[oldi->parent_vp] = true;
>>>           oldi->tidss = tidss;
>>>             drm_bridge_add(&oldi->bridge);
>>
>